Thin film transistor substrate, and display panel and display device including same

ABSTRACT

A thin film transistor substrate according to an embodiment includes: a substrate; and a thin film transistor disposed on the substrate, wherein the thin film transistor includes a channel layer including a nitride-based semiconductor layer, a source electrode electrically connected to a first region of the channel layer, a drain electrode electrically connected to a second region of the channel layer, a gate electrode disposed on the channel layer, and a depletion forming layer disposed between the channel layer and the gate electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is the National Phase of PCT International ApplicationNo. PCT/KR2016/012879, filed on Nov. 9, 2016, which claims priorityunder 35 U.S.C. 119(a) to Patent Application No. 10-2016-0003024, filedin the Republic of Korea on Jan. 11, 2016, all of which are herebyexpressly incorporated by reference into the present application.

TECHNICAL FIELD

The present invention relates to a thin film transistor substrate, and adisplay panel and a display device comprising the same.

BACKGROUND ART

According to development of the information society, demands for displaydevices for displaying images are increasing in various forms, anddemand for high-resolution display devices is also increasing. As a wayfor realizing a high-resolution display device, the number of pixels perunit area is increased, but the numbers of gate wirings and data wiringsare increased in order to supply a gate signal and a data signal inaccordance with increased pixels. However, as the number of gate wiringsincreases, a time (Gate on Time) for which a gate signal may be providedto one pixel is shortened, so that development of a thin film transistorwith a high carrier mobility is required.

In addition, as a way for smooth moving picture playback, a way forincreasing a driving frequency has been studied, and even when thedriving frequency is increased, a time (Gate on Time) for which a gatesignal may be provided to one pixel is shortened, so that development ofa thin film transistor with a high carrier mobility is required.

DISCLOSURE Technical Problem

An embodiment provides a thin film transistor substrate capable ofincreasing mobility of a carrier and ensuring product reliability, and adisplay panel and a display device comprising the same.

Technical Solution

A thin film transistor substrate according to an embodiment comprises: asubstrate; and a thin film transistor disposed on the substrate, thethin film transistor comprising a channel layer including anitride-based semiconductor layer, a source electrode electricallyconnected to a first region of the channel layer, a drain electrodeelectrically connected to a second region of the channel layer, a gateelectrode disposed on the channel layer, and a depletion forming layerdisposed between the channel layer and the gate electrode.

A display panel according to an embodiment comprises: a thin filmtransistor substrate comprising a substrate; a thin film transistordisposed on the substrate, the thin film transistor comprising a channellayer including a nitride-based semiconductor layer, a source electrodeelectrically connected to a first region of the channel layer, a drainelectrode electrically connected to a second region of the channellayer, a gate electrode disposed on the channel layer, and a depletionforming layer disposed between the channel layer and the gate electrode:a color filter substrate disposed on the thin film transistor substrate:and a liquid crystal layer provided between the thin film transistorsubstrate and the color filter substrate.

A display device according to an embodiment comprises: a display panelcomprising a thin film transistor substrate and a color filter substratedisposed on the thin film transistor substrate, the thin film transistorsubstrate comprising a substrate; a thin film transistor disposed on thesubstrate, the thin film transistor comprising a channel layer includinga nitride-based semiconductor layer, a source electrode electricallyconnected to a first region of the channel layer, a drain electrodeelectrically connected to a second region of the channel layer, a gateelectrode disposed on the channel layer, and a depletion forming layerdisposed between the channel layer and the gate electrode: and a lightunit disposed under the display panel to supply light to the displaypanel.

A thin film transistor substrate according to an embodiment comprises: asubstrate; and a thin film transistor disposed on the substrate, thethin film transistor comprising a channel layer including anitride-based semiconductor layer, a source electrode electricallyconnected to a first region of the channel layer, a drain electrodeelectrically connected to a second region of the channel layer, a firstgate electrode disposed on the channel layer, a depletion forming layerdisposed between the channel layer and the first gate electrode, and asecond gate electrode disposed under the channel layer.

A thin film transistor substrate according to an embodiment comprises: asubstrate; and a thin film transistor disposed on the substrate, thethin film transistor comprising a channel layer including anitride-based semiconductor layer and having a recessed region recessedin a downward direction on an upper surface thereof, a source electrodeelectrically connected to a first region of the upper surface of thechannel layer, a drain electrode electrically connected to a secondregion of the upper surface of the channel layer, and a gate electrodedisposed in the recessed region of the channel layer.

A thin film transistor substrate according to an embodiment comprises: asubstrate; a switching thin film transistor disposed on the substrate,the switching thin film transistor comprising a first channel layerincluding a nitride-based semiconductor layer, a first source electrodeelectrically connected to a first region of the first channel layer, afirst drain electrode electrically connected to a second region of thefirst channel layer, a first gate electrode disposed on the firstchannel layer, and a first depletion forming layer disposed between thefirst channel layer and the first gate electrode; and a driving thinfilm transistor disposed on the substrate, the driving thin filmtransistor comprising a second channel layer including a nitride-basedsemiconductor layer, a second source electrode electrically connected toa first region of the second channel layer, a second drain electrodeelectrically connected to a second region of the second channel layer, asecond gate electrode disposed on the second channel layer, and a seconddepletion forming layer disposed between the second channel layer andthe second gate electrode.

A thin film transistor substrate according to an embodiment comprises: asubstrate; a switching thin film transistor disposed on the substrate,the switching thin film transistor comprising a first channel layerincluding a nitride-based semiconductor layer, a first source electrodeelectrically connected to a first region of the first channel layer, afirst drain electrode electrically connected to a second region of thefirst channel layer, a first gate electrode disposed on the firstchannel layer, a first depletion forming layer disposed between thefirst channel layer and the first gate electrode, and a first doublegate electrode disposed under the first channel layer; and a drivingthin film transistor disposed on the substrate, the driving thin filmtransistor comprising a second channel layer including a nitride-basedsemiconductor layer, a second source electrode electrically connected toa first region of the second channel layer, a second drain electrodeelectrically connected to a second region of the second channel layer, asecond gate electrode disposed on the second channel layer, a seconddepletion forming layer disposed between the second channel layer andthe second gate electrode, and a second double gate electrode disposedunder the second channel layer.

A thin film transistor substrate according to an embodiment comprises: asubstrate; a switching thin film transistor disposed on the substrate,the switching thin film transistor comprising a first channel layerincluding a nitride-based semiconductor layer and having a firstrecessed region recessed in a downward direction on an upper surfacethereof, a first source electrode electrically connected to a firstregion of the upper surface of the first channel layer, a first drainelectrode electrically connected to a second region of the upper surfaceof the first channel layer, and a first gate electrode disposed in thefirst recessed region of the first channel layer; and a driving thinfilm transistor disposed on the substrate, the driving thin filmtransistor comprising a second channel layer including a nitride-basedsemiconductor layer and having a second recessed region recessed in adownward direction on an upper surface thereof, a second sourceelectrode electrically connected to a first region of the upper surfaceof the second channel layer, a second drain electrode electricallyconnected to a second region of the upper surface of the second channellayer, and a second gate electrode disposed in the second recessedregion of the second channel layer.

Advantageous Effects

A thin film transistor substrate according to an embodiment, and adisplay panel and a display device comprising the same, have anadvantage of realizing a high resolution and reproducing a smooth movingpicture by providing a high carrier mobility.

DESCRIPTION OF DRAWINGS

FIG. 1 is a view illustrating a thin film transistor substrate accordingto an embodiment of the present invention.

FIGS. 2 to 14 are views illustrating an example of a manufacturingprocess of the thin film transistor substrate shown in FIG. 1 accordingto an embodiment of the present invention.

FIG. 15 is a view illustrating an example in which a plurality of pixelsare disposed on a thin film transistor substrate according to anembodiment of the present invention.

FIGS. 16 and 17 are views illustrating another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 18 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 19 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 20 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 21 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 22 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 23 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 24 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIGS. 25 and 26 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention.

FIG. 27 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 28 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 29 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 30 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 31 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 32 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 33 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 34 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 35 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 36 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 37 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 38 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 39 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 40 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 41 is a block diagram illustrating an example of a display devicecomprising a thin film transistor substrate according to an embodimentof the present invention.

FIG. 42 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 43 is a cross-sectional view taken along line D-D of the thin filmtransistor substrate shown in FIG. 42 according to the embodiment of thepresent invention.

FIG. 44 is a cross-sectional view taken along line E-E of the thin filmtransistor substrate shown in FIG. 42 according to the embodiment of thepresent invention.

FIG. 45 is a circuit diagram equivalently illustrating one pixel in thethin film transistor substrate described with reference to FIGS. 42 to44.

FIG. 46 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 47 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 48 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 49 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 50 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 51 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 52 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention.

FIG. 53 is a block diagram illustrating an example of a display devicecomprising a thin film transistor substrate according to an embodimentof the present invention.

MODES OF THE INVENTION

In the description of an embodiment, when it is described that eachlayer (film), region, pattern, or structure is formed “above/on” or“below/under” a substrate, each layer (film), region, pad or pattern,the description comprises being formed both “directly” and “indirectly(by interposing another layer)” “above/on” or “below/under”. Also, astandard of above/on or below/under of each layer will be describedbased on the drawings.

Hereinafter, a thin film transistor substrate, a display panel, adisplay device, and a method of manufacturing a thin film transistorsubstrate according to embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

FIG. 1 is a view illustrating a thin film transistor substrate accordingto an embodiment of the present invention.

As shown in FIG. 1, the thin film transistor substrate according to anembodiment of the present invention may comprise a substrate 55, a thinfilm transistor 30 disposed on the substrate 55, and a pixel electrode80 electrically connected to the thin film transistor 30.

The thin film transistor 30 according to an embodiment may comprise adepletion forming layer 15, a gate electrode 33, a channel layer 60, asource electrode 71, and a drain electrode 72. The source electrode 71may be electrically connected to a first region of the channel layer 60.The source electrode 71 may be electrically connected to an uppersurface of the channel layer 60. The drain electrode 72 may beelectrically connected to a second region of the channel layer 60. Thedrain electrode 72 may be electrically connected to the upper surface ofthe channel layer 60. The gate electrode 33 may be disposed on thechannel layer 60. The depletion forming layer 15 may be disposed onbetween the first region and the second region of the channel layer 60.The depletion forming layer 15 may be disposed between the channel layer60 and the gate electrode 33.

The channel layer 60 may be provided with, for example, a Group III-Vcompound semiconductor. For example, the channel layer 60 may beprovided with a semiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The channel layer 60may comprise a single layer or multiple layers selected from, forexample, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs,GaAsP, AlGaInP and so on.

The channel layer 60 may comprise a first nitride semiconductor layer 61and a second nitride semiconductor layer 62. The first nitridesemiconductor layer 61 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layer 62 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).

According to the channel layer 60 according to an embodiment, the firstnitride semiconductor layer 61 may comprise a GaN semiconductor layer,and the second nitride semiconductor layer 62 may comprise an AlGaNsemiconductor layer. The second nitride semiconductor layer 62 may bedisposed between the first nitride semiconductor layer 61 and thedepletion forming layer 15.

The depletion forming layer 15 may be provided with, for example, aGroup III-V compound semiconductor. For example, the depletion forminglayer 15 may be provided with a semiconductor material having anempirical formula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).The depletion forming layer 15 may comprise a single layer or multiplelayers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN,AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and so on. The depletionforming layer 15 may comprise a nitride semiconductor layer doped with ap-type dopant. For example, the depletion forming layer 15 may comprisea GaN semiconductor layer doped with a p-type dopant or an AlGaNsemiconductor layer doped with a p-type dopant. The depletion forminglayer 15 may comprise a single layer or multiple layers provided with,for example, a semiconductor material having an empirical formula ofp-Al_(x)Ga_(1-x)N (0≥x≥0.3).

The depletion forming layer 15 may be provided in a thickness of 2 to300 nm as an example. The depletion forming layer 15 may be provided ina thickness of at least 2 nm in order to provide a depletion region attwo-dimensional electron gas (2 DEG) provided at the channel layer 60.In addition, the depletion forming layer 15 may be provided in athickness of 30 nm or more in consideration of a thickness deviationaccording to a manufacturing process. In addition, the depletion forminglayer 15 may be provided in a thickness of 200 nm or less inconsideration of a thickness deviation according to a manufacturingprocess. The depletion forming layer 15 may be provided in a thicknessof 50 to 100 nm as an example.

The depletion forming layer 15 may serve to form a depletion region attwo-dimensional electron gas (2 DEG) provided at the channel layer 60.The energy bandgap of a portion of the second nitride semiconductorlayer 62 positioned thereunder may be increased by the depletion forminglayer 15. As a result, the depletion region of the 2 DEG may be providedat a portion of the channel layer 60 corresponding to the depletionforming layer 15. Therefore, a region corresponding to the position inwhich the depletion forming layer 15 is disposed in the 2 DEG providedat the channel layer 60 may be cut off. The region in which the 2 DEG iscut off at the channel layer 60 may be referred to as a cut-off region.For example, a cut-off region may be formed at the second nitridesemiconductor layer 62. The thin film transistor 30 may have anormally-off characteristic due to such a cut-off region. When a voltageequal to or higher than a threshold voltage is applied to the gateelectrode 33, the 2 DEG is generated at the cut-off region and the thinfilm transistor 30 is turned on. When a channel formed at a lowerportion of the gate electrode 33 is turned on, a current may flow viathe 2 DEG formed at the channel layer 60. Accordingly, the current flowfrom the first region to the second region of the channel layer 60 maybe controlled according to a voltage applied to the gate electrode 33.

The substrate 55 may comprise a transparent substrate. The substrate 55may be provided with a transparent substrate having a thickness of 0.1mm to 3 mm as an example. In addition, the thickness of the substrate 55may be changed according to application and size of an applied displaydevice and may be selected within a thickness range of 0.4 to 1.1 mm.For example, the substrate 55 may be provided in a thickness of 0.6 to0.8 mm. The substrate 55 may comprise at least one material selectedfrom materials including silicon, glass, polyimide, and plastic. Thesubstrate 55 may comprise a flexible substrate.

The substrate 55 is a substrate to be used in a transfer process whichwill be described later, and serves to support the thin film transistor30. In addition, the thin film transistor substrate according to anembodiment may comprise a bonding layer 50 provided between thesubstrate 55 and the thin film transistor 30.

The bonding layer 50 may comprise an organic material. The bonding layer50 may be provided with a transparent material. The bonding layer 50 maybe provided with, for example, a material having a transmittance of 70%or more. The bonding layer 50 may comprise an organic insulatingmaterial. The bonding layer 50 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 50 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer50 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer50 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The thin film transistor 30 according to an embodiment may comprise asource contact portion 31 disposed on the first region of the channellayer 60 and a drain contact portion 32 disposed on the second region ofthe channel layer 60. The source contact portion 31 may be disposed incontact with the first region of the channel layer 60. The drain contactportion 32 may be disposed in contact with the second region of thechannel layer 60.

A thin film transistor 30 according to an embodiment may comprise a gatewiring 41 disposed on the gate electrode 33. The gate wiring 41 may beelectrically connected to the gate electrode 33. A lower surface of thegate wiring 41 may be disposed in contact with an upper surface of thegate electrode 33.

The source electrode 71 may be electrically connected to the sourcecontact portion 31. The source electrode 71 may be disposed in contactwith an upper surface of the source contact portion 31. For example, thesource electrode 71 may be electrically connected to a first region ofthe channel layer 60 via the source contact portion 31. The drainelectrode 72 may be electrically connected to the drain contact portion32. The drain electrode 72 may be disposed in contact with an uppersurface of the drain contact portion 32. For example, the drainelectrode 72 may be electrically connected to a second region of thechannel layer 60 via the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may beprovided with a material in ohmic contact with the channel layer 60. Thesource contact portion 31 and the drain contact portion 32 may comprisea material in ohmic contact with the second nitride semiconductor layer62. For example, the source contact portion 31 and the drain contactportion 32 may comprise a single layer or multiple layers comprising atleast one material selected from the group consisting of aluminum (Al),an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy(Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy),gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), atitanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The sourcecontact portion 31 and the drain contact portion 32 may be provided in athickness of 0.1 to 1 μm as an example. The source contact portion 31and the drain contact portion 32 do not need to serve to spread acurrent as a layer for contacting with the channel layer 60.Accordingly, the source contact portion 31 and the drain contact portion32 may be provided in a thickness of 1 μm or less.

The gate electrode 33 may be provided with a material in ohmic contactwith the depletion forming layer 15. For example, the gate electrode 33may be provided with a metallic material in ohmic contact with a p-typenitride layer. The gate electrode 33 may comprise a single layer ormultiple layers comprising at least one material selected from the groupconsisting of tungsten (W), tungsten silicon (WSi₂), titanium nitride(TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd), nickel(Ni), and platinum (Pt). The gate electrode 33 may be provided in athickness of 0.1 to 1 μm as an example. The gate electrode 33 does notneed to serve to spread a current as a layer for contacting with thedepletion forming layer 15. Accordingly, the gate electrode 33 may beprovided in a thickness of 1 μm or less.

The gate wiring 41 may comprise a single layer or multiple layerscomprising at least one material selected from the group consisting ofaluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu),a copper alloy (Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy(Ag alloy), gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium(Ti), a titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The gatewiring 41 may be provided in a thickness of 0.1 to 3 μm as an example.The gate wiring 41 serves to sequentially apply a voltage to a pluralityof transistors. Accordingly, the gate wiring 41 may be provided to bethicker than a thickness of the gate electrode 33.

The source electrode 71 and the drain electrode 72 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of aluminum (Al), an aluminum alloy (Al alloy),tungsten (W), copper (Cu), a copper alloy (Cu alloy), molybdenum (Mo),silver (Ag), a silver alloy (Ag alloy), gold (Au), a gold alloy (Aualloy), chromium (Cr), titanium (Ti), a titanium alloy (Ti alloy),molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The source electrode 71 and thedrain electrode 72 may be provided in a thickness of 0.1 to 3 μm as anexample. The source electrode 71 serves to sequentially apply a voltageto the plurality of transistors. Accordingly, the source electrode 71may be provided to be thicker than a thickness of the source contactportion 31. Also, the drain electrode 72 may be provided to be thickerthan a thickness of the drain contact portion 32.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 21 disposed on the channel layer 60.The first passivation film 21 may be disposed on the second nitridesemiconductor layer 62. A lower surface of the first passivation film 21may be disposed in contact with an upper surface of the second nitridesemiconductor layer 62. The first passivation film 21 may be disposed onthe depletion forming layer 15. The first passivation film 21 may bedisposed at a side surface of the depletion forming layer 15. The firstpassivation film 21 may be disposed so as to surround the side surfaceof the depletion forming layer 15.

According to an embodiment, the source contact portion 31 may bedisposed to pass through the first passivation film 21. The sourcecontact portion 31 may be disposed to be surrounded by the firstpassivation film 21. The source contact portion 31 may be disposed topass through the first passivation film 21 and provided in contact withthe first region of the channel layer 60. The drain contact portion 32may be disposed to pass through the first passivation film 21. The draincontact portion 32 may be disposed to be surrounded by the firstpassivation film 21. The drain contact portion 32 may be disposed topass through the first passivation film 21 and provided in contact withthe second region of the channel layer 60.

The first passivation film 21 may be provided with an insulatingmaterial. The first passivation film 21 may comprise a single layer ormultiple layers comprising at least one of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55 and the first passivation film 21. The gateelectrode 33 may be disposed to pass through at least one of the firstpassivation film 21 and the second passivation film 22. For example, thegate electrode 33 may be disposed to pass through the first passivationfilm 21 and the second passivation film 22. The gate electrode 33 maypass through at least one of the first passivation film 21 and thesecond passivation film 22 and be disposed in contact with the depletionforming layer 15. For example, the gate electrode 33 may pass throughthe first passivation film 21 and the second passivation film 22 and bedisposed in contact with the depletion forming layer 15. The gate wiring41 may be disposed on the second passivation film 22 and be electricallyconnected to the gate electrode 33. The second passivation film 22 maybe provided with an insulating material. The second passivation film 22may comprise a single layer or multiple layers including at least onematerial of a silicon-based oxide, a silicon-based nitride, a metaloxide including Al₂O₃, and an organic insulating material as an example.

According to an embodiment, a third passivation film 23 may be disposedon the second passivation film 22. The third passivation film 23 may bedisposed on the second passivation film 22 and the gate wiring 41. Thegate wiring 41 may be disposed in contact with the gate electrode 33thereon and provided to be surrounded by the third passivation film 23.

The source electrode 71 may pass through the second passivation film 22and the third passivation film 23 and be electrically connected to thesource contact portion 31. The source electrode 71 may comprise a firstregion disposed on the third passivation film 23. The source electrode71 may comprise a second region passing through the third passivationfilm 23 and the second passivation film 22. The drain electrode 72 maypass through the second passivation film 22 and the third passivationfilm 23 and be electrically connected to the drain contact portion 32.The drain electrode 72 may comprise a first region disposed on the thirdpassivation film 23. The drain electrode 72 may comprise a second regionpassing through the third passivation film 23 and the second passivationfilm 22.

The third passivation film 23 may comprise an insulating material. Thethird passivation film 23 may comprise a single layer or multiple layerscomprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 24 disposed on the third passivationfilm 23. The fourth passivation film 24 may be disposed on the sourceelectrode 71 and the drain electrode 72. The fourth passivation film 24may comprise a contact hole H3 provided on the drain electrode 72.

The fourth passivation film 24 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, the pixel electrode 80 may be disposed onthe fourth passivation film 24. The pixel electrode 80 may beelectrically connected to the drain electrode 72 via the contact hole H3provided in the fourth passivation film 24. A lower surface of the pixelelectrode 80 may be disposed in contact with an upper surface of thedrain electrode 72.

The pixel electrode 80 may be provided with a transparent conductivematerial. The pixel electrode 80 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 80 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The thin film transistor substrate according to an embodiment maycomprise a black matrix 40 between the substrate 55 and the channellayer 60. A width of the channel layer 60 may be provided to be equal toa width of the black matrix 40. The black matrix 40 may be provided in asingle layer or multiple layers including at least one material selectedfrom among a Si-based material, a Ga-based material, an Al-basedmaterial, and an organic material. The black matrix 40 may block lightincident on the thin film transistor 30. Accordingly, it is possible toprevent the thin film transistor 30 from deteriorating due to a photocurrent or the like.

According to an embodiment, the bonding layer 50 may be disposed betweenthe substrate 55 and the channel layer 60. The bonding layer 50 may bedisposed between the substrate 55 and the black matrix 40. For example,the bonding layer 50 may be disposed on an entire region of thesubstrate 55. The bonding layer 50 may be disposed in contact with thesecond passivation film 22. An upper surface of the bonding layer 50 anda lower surface of the second passivation film 22 may be disposed incontact with each other. For example, in a region where the black matrix40 is not provided, the upper surface of the bonding layer 50 and thelower surface of the second passivation film 22 may be disposed indirect contact with each other.

Hereinafter, an example of a manufacturing process of a thin filmtransistor substrate according to an embodiment of the present inventionwill be described with reference to FIGS. 2 to 14. In FIGS. 2 to 13, (a)of each drawing is a plan view and (b) of that is a cross-sectional viewtaken along line A-A of a plan view.

First, as shown in FIG. 2, a first layer 11, a second layer 12, and athird layer 13 may be sequentially grown on a growth substrate 10.

The growth substrate 10 may be a substrate on which the first layer 11,the second layer 12, and the third layer 13 may be grown. The growthsubstrate 10 may comprise at least one of sapphire, SiC, GaAs, GaN, ZnO,Si, GaP, InP and Ge as an example. A buffer layer may be further formedbetween the growth substrate 10 and the first layer 11.

The first layer 11, the second layer 12, and the third layer 13 may beprovided with, for example, a Group III-V compound semiconductor. Forexample, the first layer 11, the second layer 12, and the third layer 13may be provided with a semiconductor material having an empiricalformula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The firstlayer 11, the second layer 12, and the third layer 13 may comprise asingle layer or multiple layers selected from, for example, GaN, AlN,AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP andso on.

According to an embodiment, for example, the first layer 11 may beformed of a GaN semiconductor layer, and the second layer 12 may beformed of an AlGaN semiconductor layer. The third layer 13 may comprisea nitride semiconductor layer doped with a p-type dopant. For example,the third layer 13 may comprise a GaN semiconductor layer doped with ap-type dopant or an AlGaN semiconductor layer doped with a p-typedopant. The third layer 13 may comprise a single layer or multiplelayers provided with, for example, a semiconductor material having anempirical formula of p-Al_(x)Ga_(1-x)N (0≥x≥0.3).

Next, as shown in FIG. 3, a depletion forming layer 15 may be formed onthe second layer 12 by etching the third layer 13. The depletion forminglayer 15 may be formed, for example, by a photolithography process andan etching process.

Next, as shown in FIG. 4, a first passivation film 21 may be formed onthe second layer 12 and the depletion forming layer 15. The firstpassivation film 21 may be formed of an insulating material. The firstpassivation film 21 may comprise a single layer or multiple layerscomprising at least one material of, for example, a silicon-based oxide,a silicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material.

As shown in FIG. 5, a source contact portion 31 and a drain contactportion 32 may be formed on the second layer 12. The source contactportion 31 and the drain contact portion 32 may be formed on the secondlayer 12 by passing through the first passivation film 21. For example,the source contact portion 31 and the drain contact portion 32 may beformed by a self-align process. The source contact portion 31 and thedrain contact portion 32 may be in ohmic contact with the second layer12. For example, the source contact portion 31 and the drain contactportion 32 may comprise a single layer or multiple layers comprising atleast one material selected from the group consisting of aluminum (Al),an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy(Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy),gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), atitanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The sourcecontact portion 31 and the drain contact portion 32 may be formed in athickness of 0.1 to 1 μm as an example. Since the source contact portion31 and the drain contact portion 32 do not need to serve to spread acurrent as a layer for contacting with the channel layer 60, the sourcecontact portion 31 and the drain contact portion 32 may be provided in athickness of 1 μm or less.

As shown in (a) of FIG. 5, the source contact portion 31 may have alength of L1 in a first direction and the drain contact portion 32 mayhave a length of L2 in the first direction. The depletion forming layer15 may be formed to have a length L3 in the first direction. Forexample, a side surface of the source contact portion 31 and a sidesurface of the drain contact portion 32 may be disposed to face eachother, and the depletion forming layer 15 may be disposed to extend inone direction between the side surface of the source contact portion 31and the side surface of the drain contact portion 32. The length L3 ofthe depletion forming layer 15 disposed to extend in the one directionmay be formed longer than the side length L1 of the source contactportion 31. The length L3 of the depletion forming layer 15 may beformed longer than the side length L2 of the drain contact portion 32.Since the length of the depletion forming layer 15 disposed between thesource contact portion 31 and the drain contact portion 32 is formedlonger, when the depletion forming layer 15 is operated as a transistor,a sufficient depletion region may be formed at the channel layer by thedepletion forming layer 15. Accordingly, according to an embodiment,when a gate voltage is not applied, it is possible to prevent a currentfrom flowing from the source contact portion 31 to the drain contactportion 32. As described above, according to an embodiment, it ispossible to provide a transistor of a normally off driving.

In addition, as shown in FIG. 6, a gate electrode 33 may be formed onthe depletion forming layer 15. The gate electrode 33 may be formed topass through the first passivation film 21.

The gate electrode 33 may be provided with a material in ohmic contactwith the depletion forming layer 15. For example, the gate electrode 33may be provided with a metallic material in ohmic contact with a p-typenitride layer. The gate electrode 33 may comprise a single layer ormultiple layers comprising at least one material selected from the groupconsisting of tungsten (W), tungsten silicon (WSi₂), titanium nitride(TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd), nickel(Ni), and platinum (Pt). The gate electrode 33 may be provided in athickness of 0.1 to 1 μm as an example. Since the gate electrode 33 doesnot need to serve to spread a current as a layer for contacting with thedepletion forming layer 15, the gate electrode 33 may be provided in athickness of 1 μm or less.

Next, as shown in FIG. 7, a bonding layer 51 and a temporary substrate56 may be provided on the source contact portion 31, the drain contactportion 32, and the gate electrode 33. The bonding layer 51 and thetemporary substrate 56 are provided for applying a transfer process andremoving the growth substrate 10. And then, after the growth substrate10 is removed, a black matrix layer may be formed on the first layer 11.

In addition, as shown in FIG. 8, a bonding layer 50 and a substrate 55may be provided on the black matrix layer for applying a transferprocess, and the temporary substrate 56 is removed, and a channel layer60 and a black matrix 40 may be patterned.

The bonding layer 50 may comprise an organic material. The bonding layer50 may be provided with a transparent material. The bonding layer 50 maybe provided with, for example, a material having a transmittance of 70%or more. The bonding layer 50 may comprise an organic insulatingmaterial. The bonding layer 50 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 50 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer50 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer50 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The substrate 55 may comprise a transparent substrate. The substrate 55may be provided with a transparent substrate having a thickness of 0.1mm to 3 mm as an example. In addition, the thickness of the substrate 55may be changed according to application and size of an applied displaydevice and may be selected within a thickness range of 0.4 to 1.1 mm.For example, the substrate 55 may be provided in a thickness of 0.6 to0.8 mm. The substrate 55 may comprise at least one material selectedfrom materials including silicon, glass, polyimide, and plastic. Thesubstrate 55 may comprise a flexible substrate.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate 10 and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the substrate 55.

As shown in FIG. 8, a patterning of the first passivation film 21 may beperformed, and the channel layer 60 and the black matrix 40 may beformed.

At this time, the first layer 11 and the second layer 12 may be etchedto form the channel layer 60. The channel layer 60 may comprise a firstnitride semiconductor layer 61 and a second nitride semiconductor layer62 as an example. For example, the channel layer 60 and the depletionforming layer 15 may be formed in the same length L3. When the length ofthe depletion forming layer 15 is smaller than that of the channel layer60, a leakage current may be generated. A width of the channel layer 60may be provided to be equal to a width of the black matrix 40. A widthof the first passivation film 21 may be provided to be equal to thewidth of the channel layer 60.

Next, as shown in FIG. 9, a second passivation film 22 may be formed onthe bonding layer 50 and the first passivation film 21. The secondpassivation film 22 may comprise an insulating material. The secondpassivation film 22 may comprise a single layer or multiple layersincluding at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide including Al₂O₃, and an organicinsulating material as an example.

Then, as shown in FIG. 10, a gate wiring 41 may be formed on the secondpassivation film 22. The gate wiring 41 may be electrically connected tothe gate electrode 33.

In addition, as shown in FIG. 11, a third passivation film 23 may beformed on the second passivation film 22. The third passivation film 23may be referred to as a planarization layer or an overcoat layer. Afirst contact hole H1 may be formed to pass through the thirdpassivation film 23 and the second passivation film 22 to expose thesource contact portion 31. In addition, a second contact hole H2 may beformed to pass through the third passivation film 23 and the secondpassivation film 22 to expose the drain contact portion 32.

The third passivation film 23 may comprise an insulating material. Thethird passivation film 23 may comprise a single layer or multiple layerscomprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

In addition, as shown in FIG. 12, a source electrode 71 and a drainelectrode 72 may be formed on the third passivation film 23. A firstregion of the source electrode 71 may be formed on the third passivationfilm 23 and a second region of the source electrode 71 may be formed atthe first contact hole H1, so as to electrically be connected to thesource contact portion 31. A first region of the drain electrode 72 maybe formed on the third passivation film 23 and a second region of thedrain electrode 72 may be formed at the second contact hole H2, so as toelectrically be connected to the drain contact portion 32. In addition,a data wiring 73 connected to the source electrode 71 may be formed. Thedata wiring 73 may be disposed to be extending in one direction andintersecting with the gate wiring 41.

For example, the source electrode 71 and the drain electrode 72 maycomprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of aluminum (Al), analuminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy (Cualloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold(Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), a titaniumalloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi),and copper/molybdenum titanium (Cu/MoTi). The source electrode 71 andthe drain electrode 72 may be provided in a thickness of 0.1 to 3 μm asan example. Since the source electrode 71 serves to sequentially apply avoltage to the plurality of transistors, the source electrode 71 may beprovided to be thicker than a thickness of the source contact portion31. Also, the drain electrode 72 may be provided to be thicker than athickness of the drain contact portion 32.

As shown in FIGS. 13 and 14, a fourth passivation layer 24 may be formedon the source electrode 71 and the drain electrode 72. In addition, athird contact hole H3 may be formed at the fourth passivation film 24 toexpose the drain electrode 72.

A pixel electrode 80 may be formed on the fourth passivation film 24.The pixel electrode 80 may be electrically connected to the drainelectrode 72 through the third contact hole H3 provided in the fourthpassivation film 24.

The pixel electrode 80 may be provided with a transparent conductivematerial. The pixel electrode 80 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 80 may compriseat least one material selected among indium tin oxide (ITO), indium zincoxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The basic thin film transistor substrate according to an embodiment maybe formed by such a process. The manufacturing process described withreference to FIGS. 2 to 14 is only one example, and the process methodor the process order in each step may be modified.

FIG. 15 is a view illustrating an example in which a plurality of pixelsare disposed on a thin film transistor substrate according to anembodiment of the present invention.

As shown in FIG. 15, the thin film transistor substrate according to anembodiment may comprise a plurality of thin film transistors 30 disposedin a region in which the gate wiring 41 and the data wiring 73 intersectwith each other. The pixel electrode 80 may be disposed in a region thatis defined by the gate wiring 41 and the data wiring 73. A partialregion of the pixel electrode 80 may be disposed to be overlapped withthe gate wiring 41.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. A common electrodemay be provided at the color filter substrate, and an arrangement of theliquid crystal layer disposed between the common electrode and the pixelelectrode provided on the thin film transistor substrate may becontrolled by a difference in voltage applied therebetween, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a vertical electric field type liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.An electron mobility (cm²/Vs) of the thin film transistor variesdepending on a material used as a channel layer. For example, it isreported that an amorphous silicon semiconductor has an electronmobility of 1, an oxide semiconductor has that of 10 to 80, and apolysilicon semiconductor has that of 100 or less. However, the thinfilm transistor comprising the nitride-based semiconductor layeraccording to an embodiment has been measured to have an electronmobility of 1500. Accordingly, the thin film transistor comprising thenitride-based semiconductor layer according to an embodiment may beimplemented to have an electron mobility 15 times or higher than that ofthe thin film transistor to which the polysilicon semiconductor isapplied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 16 and 17 are views illustrating another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 16 and 17, in the description of the thinfilm transistor substrate according to an embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to15 may be omitted.

The thin film transistor substrate described with reference to FIGS. 1to 15 may be applied to a vertical electric field type liquid crystaldisplay panel. A pixel electrode 80 may be disposed on the thin filmtransistor substrate and a common electrode configured to form anelectric field in a pixel along with the pixel electrode 80 may beprovided at a separate color filter substrate, and thus a verticalelectric field type liquid crystal display panel can be realized.Meanwhile, the thin film transistor substrate described with referenceto FIGS. 16 and 17 may be applied to a horizontal electric field typeliquid crystal display panel.

As shown in FIGS. 16 and 17, the thin film transistor substrateaccording to an embodiment may comprise a pixel electrode 81, a commonelectrode 85, and a fifth passivation film 25.

The common electrode 85 may be disposed on a fourth passivation film 24.The fifth passivation film 25 may be disposed on the fourth passivationfilm 24. The fifth passivation film 25 may be disposed on the commonelectrode 85 and the fourth passivation film 24. The common electrode 85may be disposed between the fourth passivation film 24 and the fifthpassivation film 25. In addition, the fifth passivation film 25 may beprovided on a drain electrode 72 exposed through the fourth passivationfilm 24. The pixel electrode 81 may be disposed on the fifth passivationfilm 25. A partial region of the pixel electrode 81 may be electricallyconnected to the drain electrode 72 through a fourth contact hole H4provided in the fifth passivation film 25. A partial region of the pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 through the fourth contact hole H4. The pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 by passing through the fourth passivation film 24 andthe fifth passivation film 25. A partial region of the pixel electrode81 and a partial region of the common electrode 85 may be overlappedwith each other in a vertical direction.

The thin film transistor substrate according to an embodiment maycomprise a plurality of thin film transistors 30 disposed in a region inwhich a gate wiring 41 and a data wiring 73 intersect with each other.The pixel electrode 81 may be disposed at a region that is defined bythe gate wiring 41 and the data wiring 73. The pixel electrode 81 maycomprise a portion extending in a finger shape. A partial region of thepixel electrode 81 may be disposed and overlapped with the gate wiring41.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 81 may be provided with a transparent conductivematerial. The pixel electrode 81 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 81 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The fifth passivation film 25 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. In the thin filmtransistor substrate according to an embodiment, an arrangement of theliquid crystal layer may be adjusted by a difference in voltage appliedbetween the common electrode 85 and the pixel electrode 81, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a horizontal electric field type liquid crystal display panel, atransverse electric field type liquid crystal display panel, or an InPlane Switching (IPS) liquid crystal display panel. Since the liquidcrystal display panel itself has no light source, a display device maybe implemented by providing a light unit that supplies light to theliquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 18 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 18, in the description of the thin filmtransistor substrate according to an embodiment, description of a partoverlapping with those described with reference to FIGS. 1 to 17 may beomitted.

The thin film transistor substrate according to an embodiment maycomprise a pixel electrode 82, a common electrode 85, a metal layer 90,a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on a fourth passivation film 24.The pixel electrode 82 may be disposed on a fifth passivation film 25.The pixel electrode 82 may be electrically connected to a drainelectrode 72. The metal layer 90 may be provided between the pixelelectrode 82 and the drain electrode 72. The metal layer 90 may bedisposed in contact with the drain electrode 72 exposed through thefourth passivation film 24. A partial region of the pixel electrode 82may be electrically connected to the drain electrode 72 through themetal layer 90 through a fifth contact hole H5 provided in the fifthpassivation film 25.

According to an embodiment, the touch panel upper electrode 92 may beprovided on the fifth passivation film 25 and the touch panel lowerelectrode 91 may be disposed below the touch panel upper electrode 92.The touch panel lower electrode 91 may be disposed on the fourthpassivation film 24 and may be electrically connected to the commonelectrode 85. The touch panel lower electrode 91 may be disposed betweenthe common electrode 85 and the fifth passivation film 25. The touchpanel upper electrode 92 may be disposed to be overlapped with the touchpanel lower electrode 91 in a vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode91 may form an in-cell touch panel provided in the display panel.Accordingly, the thin film transistor substrate according to anembodiment may detect a contact of the display panel from outside byusing the in-cell touch panel.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 82 may be provided with a transparent conductivematerial. The pixel electrode 82 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 82 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The touch panel lower electrode 91 and the touch panel upper electrode92 may be formed of a transparent conductive material. The pixelelectrode 82 may be provided with, for example, a transparent conductiveoxide film. The pixel electrode 82 may comprise at least one materialselected from among indium tin oxide (ITO), indium zinc oxide (IZO),aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indiumzinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium galliumzinc oxide (IGZO), indium gallium tin oxide (IGTO), antimony tin oxide(ATO), gallium zinc oxide (GZO), and IZO nitride (IZON).

The in-cell touch panel-integrated thin film transistor substrateaccording to an embodiment may be bonded to a color filter substrate toprovide a liquid crystal display panel. A liquid crystal layer may beprovided between the in-cell touch panel-integrated thin film transistorsubstrate and the color filter substrate. In the in-cell touchpanel-integrated thin film transistor substrate according to anembodiment, an arrangement of the liquid crystal layer may be adjustedby a difference in voltage applied between the common electrode 85 andthe pixel electrode 82, and a light transmission amount of acorresponding pixel may be controlled. The in-cell touchpanel-integrated liquid crystal display panel having such a structuremay be referred to as a horizontal electric field type liquid crystaldisplay panel, a transverse electric field type liquid crystal displaypanel, or an In Plane Switching (IPS) liquid crystal display panel.Since the in-cell touch panel-integrated liquid crystal display panelitself has no light source, a display device may be implemented byproviding a light unit that supplies light to the in-cell touchpanel-integrated liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 19 to 21 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 19 to 21, in the description of the thinfilm transistor substrate according to an embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to18 may be omitted. An embodiment shown in FIGS. 19 to 21 differs fromthat of each of FIGS. 1, 16, and 18 in the bonding layer structure.

As shown in FIGS. 19 to 21, a bonding layer 53 may be provided on thesubstrate 55. The bonding layer 53 may be disposed between the substrate55 and the black matrix 40. For example, a width of the bonding layer 53may be provided to be equal to a width of the black matrix 40. Forexample, the width of the bonding layer 53 may be provided to be equalto a width of the channel layer 60.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55. A lower surface of the second passivation film 22may be disposed in contact with an upper surface of the substrate 55. Ina region where the bonding layer 50 is not provided, the secondpassivation film 22 may be disposed in direct contact with the substrate55.

As described above, according to the embodiment shown in FIGS. 19 to 21,as compared with the embodiment shown in FIGS. 1, 16, and 18, since thesecond passivation film 22 and the substrate 55 may be disposed indirect contact with each other, a layer provided between the secondpassivation film 22 and the substrate 55 (for example, an illustratedbonding layer in FIGS. 1, 16, and 18) may be eliminated. Accordingly,according to the embodiment, since an interface between differentmaterial layers is reduced on a light path where light travels, lightloss due to reflection/refraction at the interface may be reduced.

The bonding layer 53 according to an embodiment may comprise at leastone of a reflective layer, a metal bonding layer, an organic bondinglayer, and an insulating layer as an example. The reflective layer maybe disposed on the substrate 55, the metal bonding layer may be disposedon the reflective layer, and the insulating layer may be disposed on themetal bonding layer. For example, the bonding layer 53 may comprise atleast one of the metal bonding layer and the organic bonding layer, andthe reflective layer and the insulating layer may be comprisedselectively.

The insulating layer may complement the leakage characteristics of thechannel layer 60. For example, the insulating layer may comprise asingle layer or multiple layers including at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide includingAl₂O₃, and an organic insulating material as an example.

The metal bonding layer or the organic bonding layer may be provided forbonding with the substrate 55 disposed thereunder. For example, themetal bonding layer may comprise at least one material selected from thegroup consisting of gold (Au), tin (Sn), indium (In), nickel (Ni),silver (Ag), and copper (Cu), or an alloy thereof. For example, theorganic bonding layer may comprise at least one material selected fromthe group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, andthe like.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

Meanwhile, according to an embodiment, for example, when the bondinglayer 53 comprises the metal bonding layer and the reflective layer, theblack matrix 40 may be omitted.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 22 to 24 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 22 to 24, in the description of the thinfilm transistor substrate according to the embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to21 may be omitted. An embodiment shown in FIGS. 22 to 24 differs fromthat of each of FIGS. 1, 16, and 18 in that a transfer process is notapplied and a thin film transistor is provided on a growth substrate.

As shown in FIGS. 22 to 24, the thin film transistor substrate accordingto the embodiment may comprise a growth substrate 10 as a substrateinstead of a support substrate used in the transfer process. Forexample, the growth substrate 10 may comprise at least one of sapphire,SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

A black matrix 45 may be disposed on the growth substrate 10. The blackmatrix 45 is disposed on the growth substrate 10 and may prevent lightfrom being incident on the channel layer 60. The black matrix 45 may beprovided with a material that absorbs or reflects visible rays as anexample. Thus, according to the embodiment, light is incident on thechannel layer 60 and it is possible to prevent a thin film transistor 30from being deteriorated due to a photo current or the like. For example,the black matrix 45 may be provided in a single layer or multiple layersincluding at least one material selected from among a Si-based material,a Ga-based material, an Al-based material, and an organic material. Theblack matrix 45 may selectively comprise a material such as Si, GaAs, orthe like.

According to an embodiment, a buffer layer 47 may be provided on theblack matrix 45. The buffer layer 47 may be provided between the blackmatrix 45 and the channel layer 60. The buffer layer 47 may help agrowth of a nitride semiconductor layer constituting the channel layer60. For example, the buffer layer 47 may comprise a single layer ormultiple layers including at least one material selected from the groupconsisting of AlN, AlInN, and AlGaN.

For example, a width of the black matrix 45 may be provided to be equalto a width of the buffer layer 47. For example, the width of the blackmatrix 45 may be provided to be equal to a width of the channel layer60. The width of the buffer layer 47 may be provided to be equal to thewidth of the channel layer 60.

According to an embodiment, the second passivation film 22 may bedisposed on the growth substrate 10. A lower surface of the secondpassivation film 22 may be disposed in contact with an upper surface ofthe growth substrate 10. In a region where the black matrix 45 is notprovided, the second passivation film 22 may be disposed in directcontact with the growth substrate 10.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 25 and 26 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIGS. 25 and 26is an embodiment to which a thin film transistor having a double gatestructure is applied, and description of contents overlapping with thosedescribed with reference to FIGS. 1 to 24 may be omitted.

As shown in FIGS. 25 and 26, the thin film transistor substrateaccording to an embodiment of the present invention may comprise asubstrate 55, a thin film transistor 130 disposed on the substrate 55,and a pixel electrode 80 electrically connected to the thin filmtransistor 130.

The thin film transistor 130 according to an embodiment may comprise adepletion forming layer 15, a first gate electrode 35, a second gateelectrode 36, a channel layer 60, a source electrode 71, and a drainelectrode 72. The source electrode 71 may be electrically connected to afirst region of the channel layer 60. The source electrode 71 may beelectrically connected to an upper surface of the channel layer 60. Thedrain electrode 72 may be electrically connected to a second region ofthe channel layer 60. The drain electrode 72 may be electricallyconnected to the upper surface of the channel layer 60. The first gateelectrode 35 may be disposed on the channel layer 60. The second gateelectrode 36 may be disposed under the channel layer 60. The depletionforming layer 15 may be disposed on between the first region and thesecond region of the channel layer 60. The depletion forming layer 15may be disposed between the channel layer 60 and the first gateelectrode 35.

The channel layer 60 may be provided with, for example, a Group III-Vcompound semiconductor. For example, the channel layer 60 may beprovided with a semiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The channel layer 60may comprise a single layer or multiple layers selected from, forexample, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs,GaAsP, AlGaInP and so on.

The channel layer 60 may comprise a first nitride semiconductor layer 61and a second nitride semiconductor layer 62. The first nitridesemiconductor layer 61 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layer 62 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).

According to the channel layer 60 according to an embodiment, the firstnitride semiconductor layer 61 may comprise a GaN semiconductor layer,and the second nitride semiconductor layer 62 may comprise an AlGaNsemiconductor layer. The second nitride semiconductor layer 62 may bedisposed between the first nitride semiconductor layer 61 and thedepletion forming layer 15.

The depletion forming layer 15 may be provided with, for example, aGroup III-V compound semiconductor. For example, the depletion forminglayer 15 may be provided with a semiconductor material having anempirical formula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).The depletion forming layer 15 may comprise a single layer or multiplelayers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN,AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and so on. The depletionforming layer 15 may comprise a nitride semiconductor layer doped with ap-type dopant. For example, the depletion forming layer 15 may comprisea GaN semiconductor layer doped with a p-type dopant or an AlGaNsemiconductor layer doped with a p-type dopant. The depletion forminglayer 15 may comprise a single layer or multiple layers provided with,for example, a semiconductor material having an empirical formula ofp-Al_(x)Ga_(1-x)N (0≥x≥0.3).

The depletion forming layer 15 may be provided in a thickness of 2 to300 nm as an example. The depletion forming layer 15 may be provided ina thickness of at least 2 nm in order to provide a depletion region attwo-dimensional electron gas (2 DEG) provided at the channel layer 60.In addition, the depletion forming layer 15 may be provided in athickness of 30 nm or more in consideration of a thickness deviationaccording to a manufacturing process. In addition, the depletion forminglayer 15 may be provided in a thickness of 200 nm or less inconsideration of a thickness deviation according to a manufacturingprocess. The depletion forming layer 15 may be provided in a thicknessof 50 to 100 nm as an example.

The depletion forming layer 15 may serve to form a depletion region attwo-dimensional electron gas (2 DEG) provided at the channel layer 60.The energy bandgap of a portion of the second nitride semiconductorlayer 62 positioned thereon may be increased by the depletion forminglayer 15. As a result, the depletion region of the 2 DEG may be providedat a portion of the channel layer 60 corresponding to the depletionforming layer 15. Therefore, a region corresponding to the position inwhich the depletion forming layer 15 is disposed in the 2 DEG providedat the channel layer 60 may be cut off. The region in which the 2 DEG iscut off at the channel layer 60 may be referred to as a cut-off region.For example, a cut-off region may be formed at the second nitridesemiconductor layer 62. The thin film transistor 130 may have anormally-off characteristic due to such a cut-off region. When a voltageequal to or higher than a threshold voltage is applied to the first gateelectrode 35, the 2 DEG is generated at the cut-off region and the thinfilm transistor 130 is turned on. When a channel formed at a lowerportion of the first gate electrode 35 is turned on, a current may flowvia the 2 DEG formed at the channel layer 60. Accordingly, the currentflow from the first region to the second region of the channel layer 60may be controlled according to a voltage applied to the first gateelectrode 35 and the second gate electrode 36. Meanwhile, according tothe present embodiment, the second gate electrode 36 may be disposedunder the channel layer 60. The first gate electrode 35 and the secondgate electrode 36 may be disposed to be overlapped with each other in avertical direction. According to an embodiment, the first gate electrode35 and the second gate electrode 36 are disposed above and below thechannel layer 60 to efficiently and reliably control a current flow inthe channel layer 60.

The substrate 55 may comprise a transparent substrate. The substrate 55may be provided with a transparent substrate having a thickness of 0.1mm to 3 mm as an example. In addition, the thickness of the substrate 55may be changed according to application and size of an applied displaydevice and may be selected within a thickness range of 0.4 to 1.1 mm.For example, the substrate 55 may be provided in a thickness of 0.6 to0.8 mm. The substrate 55 may comprise at least one material selectedfrom materials including silicon, glass, polyimide, and plastic. Thesubstrate 55 may comprise a flexible substrate

The substrate 55 is a substrate to be used in a transfer process, andserves to support the thin film transistor 130. In addition, the thinfilm transistor substrate according to an embodiment may comprise abonding layer 50 provided between the substrate 55 and the thin filmtransistor 130.

The bonding layer 50 may comprise an organic material. The bonding layer50 may be provided with a transparent material. The bonding layer 50 maybe provided with, for example, a material having a transmittance of 70%or more. The bonding layer 50 may comprise an organic insulatingmaterial. The bonding layer 50 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 50 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer50 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer50 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The thin film transistor 30 according to an embodiment may comprise asource contact portion 31 disposed on the first region of the channellayer 60 and a drain contact portion 32 disposed on the second region ofthe channel layer 60. The source contact portion 31 may be disposed incontact with the first region of the channel layer 60. The drain contactportion 32 may be disposed in contact with the second region of thechannel layer 60.

A thin film transistor 130 according to an embodiment may comprise agate wiring 41 disposed on the first gate electrode 35. The gate wiring41 may be electrically connected to the first gate electrode 35. A lowersurface of the gate wiring 41 may be disposed in contact with an uppersurface of the first gate electrode 35.

The source electrode 71 may be electrically connected to the sourcecontact portion 31. The source electrode 71 may be disposed in contactwith an upper surface of the source contact portion 31. For example, thesource electrode 71 may be electrically connected to a first region ofthe channel layer 60 via the source contact portion 31. The drainelectrode 72 may be electrically connected to the drain contact portion32. The drain electrode 72 may be disposed in contact with an uppersurface of the drain contact portion 32. For example, the drainelectrode 72 may be electrically connected to a second region of thechannel layer 60 via the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may beprovided with a material in ohmic contact with the channel layer 60. Thesource contact portion 31 and the drain contact portion 32 may comprisea material in ohmic contact with the second nitride semiconductor layer62. For example, the source contact portion 31 and the drain contactportion 32 may comprise a single layer or multiple layers comprising atleast one material selected from the group consisting of aluminum (Al),an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy(Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy),gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), atitanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The sourcecontact portion 31 and the drain contact portion 32 may be provided in athickness of 0.1 to 1 μm as an example. Since the source contact portion31 and the drain contact portion 32 do not need to serve to spread acurrent as a layer for contacting with the channel layer 60, the sourcecontact portion 31 and the drain contact portion 32 may be provided in athickness of 1 μm or less.

The first gate electrode 35 may be provided with a material in ohmiccontact with the depletion forming layer 15. For example, the first gateelectrode 35 may be provided with a metallic material in ohmic contactwith a p-type nitride layer. The first gate electrode 35 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of tungsten (W), tungsten silicon(WSi₂), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN),palladium (Pd), nickel (Ni), and platinum (Pt). The first gate electrode35 may be provided in a thickness of 0.1 to 1 μm as an example. Sincethe first gate electrode 35 does not need to serve to spread a currentas a layer for contacting with the depletion forming layer 15, the firstgate electrode 35 may be provided in a thickness of 1 μm or less.

The gate wiring 41 may comprise a single layer or multiple layerscomprising at least one material selected from the group consisting ofaluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu),a copper alloy (Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy(Ag alloy), gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium(Ti), a titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The gatewiring 41 may be provided in a thickness of 0.1 to 3 μm as an example.Since the gate wiring 41 serves to sequentially apply a voltage to aplurality of transistors, the gate wiring 41 may be provided to bethicker than a thickness of the gate electrode 33.

The source electrode 71 and the drain electrode 72 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of aluminum (Al), an aluminum alloy (Al alloy),tungsten (W), copper (Cu), a copper alloy (Cu alloy), molybdenum (Mo),silver (Ag), a silver alloy (Ag alloy), gold (Au), a gold alloy (Aualloy), chromium (Cr), titanium (Ti), a titanium alloy (Ti alloy),molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The source electrode 71 and thedrain electrode 72 may be provided in a thickness of 0.1 to 3 μm as anexample. Since the source electrode 71 serves to sequentially apply avoltage to the plurality of transistors, the source electrode 71 may beprovided to be thicker than a thickness of the source contact portion31. Also, the drain electrode 72 may be provided to be thicker than athickness of the drain contact portion 32.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 21 disposed on the channel layer 60.The first passivation film 21 may be disposed on the second nitridesemiconductor layer 62. A lower surface of the first passivation film 21may be disposed in contact with an upper surface of the second nitridesemiconductor layer 62. The first passivation film 21 may be disposed onthe depletion forming layer 15. The first passivation film 21 may bedisposed at a side surface of the depletion forming layer 15. The firstpassivation film 21 may be disposed so as to surround the side surfaceof the depletion forming layer 15.

According to an embodiment, the source contact portion 31 may bedisposed to pass through the first passivation film 21. The sourcecontact portion 31 may be disposed to be surrounded by the firstpassivation film 21. The source contact portion 31 may be disposed topass through the first passivation film 21 and provided in contact withthe first region of the channel layer 60. The drain contact portion 32may be disposed to pass through the first passivation film 21. The draincontact portion 32 may be disposed to be surrounded by the firstpassivation film 21. The drain contact portion 32 may be disposed topass through the first passivation film 21 and provided in contact withthe second region of the channel layer 60.

The first passivation film 21 may be provided with an insulatingmaterial. The first passivation film 21 may comprise a single layer ormultiple layers comprising at least one of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55 and the first passivation film 21. The first gateelectrode 35 may be disposed to pass through at least one of the firstpassivation film 21 and the second passivation film 22. For example, thefirst gate electrode 35 may be disposed to pass through the firstpassivation film 21 and the second passivation film 22. The first gateelectrode 35 may pass through at least one of the first passivation film21 and the second passivation film 22 and be disposed in contact withthe depletion forming layer 15. For example, the first gate electrode 35may pass through the first passivation film 21 and the secondpassivation film 22 and be disposed in contact with the depletionforming layer 15. The gate wiring 41 may be disposed on the secondpassivation film 22 and be electrically connected to the first gateelectrode 35. The second passivation film 22 may be provided with aninsulating material. The second passivation film 22 may comprise asingle layer or multiple layers including at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide includingAl₂O₃, and an organic insulating material as an example.

According to an embodiment, a third passivation film 23 may be disposedon the second passivation film 22. The third passivation film 23 may bedisposed on the second passivation film 22 and the gate wiring 41. Thegate wiring 41 may be disposed in contact with the first gate electrode35 thereon and provided to be surrounded by the third passivation film23.

The source electrode 71 may pass through the second passivation film 22and the third passivation film 23 and be electrically connected to thesource contact portion 31. The source electrode 71 may comprise a firstregion disposed on the third passivation film 23. The source electrode71 may comprise a second region passing through the third passivationfilm 23 and the second passivation film 22. The drain electrode 72 maypass through the second passivation film 22 and the third passivationfilm 23 and be electrically connected to the drain contact portion 32.The drain electrode 72 may comprise a first region disposed on the thirdpassivation film 23. The drain electrode 72 may comprise a second regionpassing through the third passivation film 23 and the second passivationfilm 22.

The second gate electrode 36 may be disposed under the channel layer 60.The second gate electrode 36 may be disposed under the first nitridesemiconductor layer 61. A sixth passivation film 26 may be disposedunder the second gate electrode 36 and the channel layer 60. The secondgate electrode 36 may be disposed in contact with a lower surface of thechannel layer 60. The second gate electrode 36 may be in Schottkycontact with the first nitride semiconductor layer 61. The second gateelectrode 36 may comprise a single layer or multiple layers including atleast one material selected from the group consisting of nickel (Ni),platinum (Pt), gold (Au), and palladium (Pd), or an alloy thereof. Forexample, the Schottky contact may be implemented by plasma treatment ofthe channel layer 60.

The first gate electrode 35 and the second gate electrode 36 may beelectrically connected as shown in FIG. 26. The thin film transistor 130according to an embodiment may be disposed on the second passivationfilm 22, and comprise a gate connecting wiring 38 electrically connectedto the first gate electrode 35 and disposed to be extending from thegate wiring 41. The gate connecting wiring 38 may be electricallyconnected to the second gate electrode 36 by passing through the secondpassivation film 22. For example, the first gate electrode 35 and thegate wiring 41 may be integrally formed in the same process. Further,the first gate electrode 35 and the gate wiring 41 may be separatelyformed in different processes and electrically connected to each other.

As shown in FIG. 26, the channel layer 60 and the depletion forminglayer 15 may be formed at the same width. When the width of thedepletion forming layer 15 is smaller than that of the channel layer 60,a leakage current may be generated. In other words, the length of thechannel layer 60 and the length of the depletion forming layer 15provided along the extending direction of the gate electrode 35 may beprovided as the same.

The third passivation film 23 may comprise an insulating material. Thethird passivation film 23 may comprise a single layer or multiple layerscomprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 24 disposed on the third passivationfilm 23. The fourth passivation film 24 may be disposed on the sourceelectrode 71 and the drain electrode 72. The fourth passivation film 24may be disposed on the first gate electrode 35. The fourth passivationfilm 24 may comprise a contact hole H3 provided on the drain electrode72.

The fourth passivation film 24 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, the pixel electrode 80 may be disposed onthe fourth passivation film 24. The pixel electrode 80 may beelectrically connected to the drain electrode 72 via the contact hole H3provided in the fourth passivation film 24. A lower surface of the pixelelectrode 80 may be disposed in contact with an upper surface of thedrain electrode 72.

The pixel electrode 80 may be provided with a transparent conductivematerial. The pixel electrode 80 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 80 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The thin film transistor substrate according to an embodiment maycomprise a black matrix 46 between the substrate 55 and the channellayer 60. The black matrix 46 may be disposed between the substrate 55and the sixth passivation film 26. The black matrix 46 may be disposedbetween the substrate 55 and the second gate electrode 36. The blackmatrix 46 may be disposed in a shape corresponding to a shape of a lowerportion of the sixth passivation film 26. A width of the channel layer60 may be provided to be equal to a width of the black matrix 46. Theblack matrix 46 may be provided in a single layer or multiple layersincluding at least one material selected from among an Si-basedmaterial, a Ga-based material, an Al-based material, and an organicmaterial. The black matrix 46 may block light incident on the thin filmtransistor 130. Accordingly, it is possible to prevent the thin filmtransistor 130 from deteriorating due to a photo current or the like.

According to an embodiment, the bonding layer 50 may be disposed betweenthe substrate 55 and the channel layer 60. The bonding layer 50 may bedisposed between the substrate 55 and the black matrix 46. For example,the bonding layer 50 may be disposed on an entire region of thesubstrate 55. The bonding layer 50 may be disposed in contact with thesecond passivation film 22. An upper surface of the bonding layer 50 anda lower surface of the second passivation film 22 may be disposed incontact with each other. For example, in a region where the black matrix46 is not provided, the upper surface of the bonding layer 50 and thelower surface of the second passivation film 22 may be disposed indirect contact with each other.

In addition, according to an embodiment, a recess corresponding to aheight and a width of the second gate electrode 36 may be provided onthe substrate 55 or the bonding layer 50. A part of the sixthpassivation film 26 may be disposed in at least a part of an upperportion and a side surface so as to correspond to a cross sectionalshape of the second gate electrode 36, and provided in the recessedregion. The black matrix 46 may be disposed in a shape corresponding toa shape of a lower portion of the sixth passivation film 26, and atleast a part of the black matrix 46 may be disposed in the recessedregion. At least a part of the second gate electrode 36 may be disposedin the recessed region. It is possible to minimize an increase in athickness of the thin film transistor substrate according to providingthe second gate electrode 36 with such a structure.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. A common electrodemay be provided at the color filter substrate. An arrangement of theliquid crystal layer disposed between the common electrode and the pixelelectrode provided on the thin film transistor substrate may be adjustedby a difference in voltage applied therebetween, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a vertical electric field type liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 27 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIG. 27 is anembodiment in which a thin film transistor having a double gatestructure is applied, and description of contents overlapping with thosedescribed with reference to FIGS. 1 to 26 may be omitted.

The thin film transistor substrate described with reference to FIGS. 25and 26 may be applied to a vertical electric field type liquid crystaldisplay panel. A pixel electrode 80 may be disposed on the thin filmtransistor substrate and a common electrode configured to form anelectric field in a pixel along with the pixel electrode 80 may beprovided at a separate color filter substrate, and thus a verticalelectric field type liquid crystal display panel can be realized.Meanwhile, the thin film transistor substrate described with referenceto FIG. 27 may be applied to a horizontal electric field type liquidcrystal display panel.

As shown in FIG. 27, the thin film transistor substrate according to anembodiment may comprise a pixel electrode 81, a common electrode 85, anda fifth passivation film 25.

The common electrode 85 may be disposed on a fourth passivation film 24.The fifth passivation film 25 may be disposed on the fourth passivationfilm 24. The fifth passivation film 25 may be disposed on the commonelectrode 85 and the fourth passivation film 24. The common electrode 85may be disposed between the fourth passivation film 24 and the fifthpassivation film 25. In addition, the fifth passivation film 25 may beprovided on a drain electrode 72 exposed through the fourth passivationfilm 24. The pixel electrode 81 may be disposed on the fifth passivationfilm 25. A partial region of the pixel electrode 81 may be electricallyconnected to the drain electrode 72 through a fourth contact hole H4provided in the fifth passivation film 25. A partial region of the pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 through the fourth contact hole H4. The pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 by passing through the fourth passivation film 24 andthe fifth passivation film 25. A partial region of the pixel electrode81 and a partial region of the common electrode 85 may be overlappedwith each other in a vertical direction.

The thin film transistor substrate according to an embodiment maycomprise a plurality of thin film transistors 130 disposed in a regionin which a gate wiring 41 and a data wiring 73 intersect with eachother. The pixel electrode 81 may be disposed at a region that isdefined by the gate wiring 41 and the data wiring 73. The pixelelectrode 81 may comprise a portion extending in a finger shape. Apartial region of the pixel electrode 81 may be disposed and overlappedwith the gate wiring 41.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 81 may be provided with a transparent conductivematerial. The pixel electrode 81 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 81 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The fifth passivation film 25 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. In the thin filmtransistor substrate according to an embodiment, an arrangement of theliquid crystal layer may be adjusted by a difference in voltage appliedbetween the common electrode 85 and the pixel electrode 81, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a horizontal electric field type liquid crystal display panel, atransverse electric field type liquid crystal display panel, or an InPlane Switching (IPS) liquid crystal display panel. Since the liquidcrystal display panel itself has no light source, a display device maybe implemented by providing a light unit that supplies light to theliquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 28 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIG. 28 is anembodiment to which a thin film transistor having a double gatestructure is applied, and description of a part overlapping with thosedescribed with reference to FIGS. 1 to 27 may be omitted.

The thin film transistor substrate according to an embodiment maycomprise a pixel electrode 82, a common electrode 85, a metal layer 90,a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on a fourth passivation film 24.The pixel electrode 82 may be disposed on a fifth passivation film 25.The pixel electrode 82 may be electrically connected to a drainelectrode 72. The metal layer 90 may be provided between the pixelelectrode 82 and the drain electrode 72. The metal layer 90 may bedisposed in contact with the drain electrode 72 exposed through thefourth passivation film 24. A partial region of the pixel electrode 82may be electrically connected to the drain electrode 72 through themetal layer 90 through a fifth contact hole H5 provided in the fifthpassivation film 25.

According to an embodiment, the touch panel upper electrode 92 may beprovided on the fifth passivation film 25 and the touch panel lowerelectrode 91 may be disposed below the touch panel upper electrode 92.The touch panel lower electrode 91 may be disposed on the fourthpassivation film 24 and may be electrically connected to the commonelectrode 85. The touch panel lower electrode 91 may be disposed betweenthe common electrode 85 and the fifth passivation film 25. The touchpanel upper electrode 92 may be disposed to be overlapped with the touchpanel lower electrode 91 in a vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode91 may form an in-cell touch panel provided in the display panel.Accordingly, the thin film transistor substrate according to anembodiment may detect a contact of the display panel from outside byusing the in-cell touch panel.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 82 may be provided with a transparent conductivematerial. The pixel electrode 82 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 82 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The touch panel lower electrode 91 and the touch panel upper electrode92 may be formed of a transparent conductive material. The pixelelectrode 82 may be provided with, for example, a transparent conductiveoxide film. The pixel electrode 82 may comprise at least one materialselected from among indium tin oxide (ITO), indium zinc oxide (IZO),aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indiumzinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium galliumzinc oxide (IGZO), indium gallium tin oxide (IGTO), antimony tin oxide(ATO), gallium zinc oxide (GZO), and IZO nitride (IZON).

The in-cell touch panel-integrated thin film transistor substrateaccording to an embodiment may be bonded to a color filter substrate toprovide a liquid crystal display panel. A liquid crystal layer may beprovided between the in-cell touch panel-integrated thin film transistorsubstrate and the color filter substrate. In the in-cell touchpanel-integrated thin film transistor substrate according to anembodiment, an arrangement of the liquid crystal layer may be adjustedby a difference in voltage applied between the common electrode 85 andthe pixel electrode 82, and a light transmission amount of acorresponding pixel may be controlled. The in-cell touchpanel-integrated liquid crystal display panel having such a structuremay be referred to as a horizontal electric field type liquid crystaldisplay panel, a transverse electric field type liquid crystal displaypanel, or an In Plane Switching (IPS) liquid crystal display panel.Since the in-cell touch panel-integrated liquid crystal display panelitself has no light source, a display device may be implemented byproviding a light unit that supplies light to the in-cell touchpanel-integrated liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 29 to 31 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 29 to 31, in the description of the thinfilm transistor substrate according to an embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to28 may be omitted. An embodiment shown in FIGS. 29 to 31 differs fromthat of each of FIGS. 19, 20, and 20 in the bonding layer structure.

As shown in FIGS. 29 to 31, a bonding layer 53 may be provided on thesubstrate 55. The bonding layer 53 may be disposed between the substrate55 and the black matrix 46. For example, a width of the bonding layer 53may be provided to be equal to a width of the black matrix 46. Forexample, the width of the bonding layer 53 may be provided to be equalto a width of the channel layer 60.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55. A lower surface of the second passivation film 22may be disposed in contact with an upper surface of the substrate 55. Ina region where the bonding layer 50 is not provided, the secondpassivation film 22 may be disposed in direct contact with the substrate55.

In addition, according to an embodiment, a recess corresponding to aheight and a width of the second gate electrode 36 may be provided onthe bonding layer 50. A part of the sixth passivation film 26 may bedisposed in at least a part of an upper portion and a side surface so asto correspond to a cross sectional shape of the second gate electrode36, and provided in the recessed region. The black matrix 46 may bedisposed in a shape corresponding to a shape of a lower portion of thesixth passivation film 26, and at least a part of the black matrix 46may be disposed in the recessed region. At least a part of the secondgate electrode 36 may be disposed in the recessed region. It is possibleto minimize an increase in a thickness of the thin film transistorsubstrate according to providing the second gate electrode 36 with sucha structure.

As described above, according to the embodiment shown in FIGS. 29 to 31,as compared with the embodiment shown in FIGS. 19, 20, and 21, since thesecond passivation film 22 and the substrate 55 may be disposed indirect contact with each other, a layer provided between the secondpassivation film 22 and the substrate 55 (for example, an illustratedbonding layer in FIGS. 19, 20, and 21) may be eliminated. Accordingly,according to the embodiment, since an interface between differentmaterial layers is reduced on a light path where light travels, lightloss due to reflection/refraction at the interface may be reduced.

The bonding layer 53 according to an embodiment may comprise at leastone of a reflective layer, a metal bonding layer, and an insulatinglayer as an example. The reflective layer may be disposed on thesubstrate 55, the metal bonding layer may be disposed on the reflectivelayer, and the insulating layer may be disposed on the metal bondinglayer. For example, the bonding layer 53 may comprise the metal bondinglayer, and the reflective layer and the insulating layer may becomprised selectively.

The insulating layer may complement the leakage characteristics of thechannel layer 60. For example, the insulating layer may comprise asingle layer or multiple layers including at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide includingAl₂O₃, and an organic insulating material as an example.

The metal bonding layer may be provided for bonding with the substrate55 disposed thereunder. For example, the metal bonding layer maycomprise at least one material selected from the group consisting ofgold (Au), tin (Sn), indium (In), nickel (Ni), silver (Ag), and copper(Cu), or an alloy thereof.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 32 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIG. 32 is anembodiment to which a thin film transistor having a structure in whichgates are disposed in a recessed region of a channel layer is applied,and description of contents overlapping with those described withreference to FIGS. 1 to 31 may be omitted.

As shown in FIG. 32, the thin film transistor substrate according to anembodiment of the present invention may comprise a substrate 55, a thinfilm transistor 230 disposed on the substrate 55, and a pixel electrode80 electrically connected to the thin film transistor 230.

The thin film transistor 230 according to an embodiment may comprise agate electrode 233, a channel layer 260, a source electrode 71, and adrain electrode 72. The source electrode 71 may be electricallyconnected to a first region of the channel layer 260. The sourceelectrode 71 may be electrically connected to an upper surface of thechannel layer 260. The drain electrode 72 may be electrically connectedto a second region of the channel layer 260. The drain electrode 72 maybe electrically connected to the upper surface of the channel layer 260.The gate electrode 233 may be disposed on the channel layer 260.

The channel layer 260 may comprise a recessed region recessed in adownward direction in the upper surface thereof. The gate electrode 233may be disposed in the recessed region of the channel layer 260.

The channel layer 260 may be provided with, for example, a Group III-Vcompound semiconductor. For example, the channel layer 260 may beprovided with a semiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≤y≥1, 0≥x+y≥1). The channel layer 260may comprise a single layer or multiple layers selected from, forexample, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs,GaAsP, AlGaInP and so on.

The channel layer 260 may comprise a first nitride semiconductor layer261 and a second nitride semiconductor layer 262. The first nitridesemiconductor layer 261 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layer 262 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). A recessed regionrecessed downwardly may be provided at an upper surface of the secondnitride semiconductor layer 262. The gate electrode 233 may be disposedin the recessed region of the second nitride semiconductor layer 262. Anupper surface of the gate electrode 233 may be disposed higher than thelowest surface of the second nitride semiconductor layer 262. The gateelectrode 233 and the second nitride semiconductor layer 262 may be inSchottky contact with each other.

According to the channel layer 260 according to an embodiment, the firstnitride semiconductor layer 261 may comprise a GaN semiconductor layer,and the second nitride semiconductor layer 262 may comprise an AlGaNsemiconductor layer.

The substrate 55 may comprise a transparent substrate. The substrate 55may be provided with a transparent substrate having a thickness of 0.1mm to 3 mm as an example. In addition, the thickness of the substrate 55may be changed according to application and size of an applied displaydevice and may be selected within a thickness range of 0.4 to 1.1 mm.For example, the substrate 55 may be provided in a thickness of 0.6 to0.8 mm. The substrate 55 may comprise at least one material selectedfrom materials including silicon, glass, polyimide, and plastic. Thesubstrate 55 may comprise a flexible substrate.

The substrate 55 is a substrate to be used in a transfer process, andserves to support the thin film transistor 230. In addition, the thinfilm transistor substrate according to an embodiment may comprise abonding layer 50 provided between the substrate 55 and the thin filmtransistor 230.

The bonding layer 50 may comprise an organic material. The bonding layer50 may be provided with a transparent material. The bonding layer 50 maybe provided with, for example, a material having a transmittance of 70%or more. The bonding layer 50 may comprise an organic insulatingmaterial. The bonding layer 50 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 50 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer50 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer50 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The thin film transistor 230 according to an embodiment may comprise asource contact portion 31 disposed on the first region of the channellayer 60 and a drain contact portion 32 disposed on the second region ofthe channel layer 60. The source contact portion 31 may be disposed incontact with the first region of the channel layer 60. The drain contactportion 32 may be disposed in contact with the second region of thechannel layer 260.

A thin film transistor 230 according to an embodiment may comprise agate wiring 41 disposed on the gate electrode 233. The gate wiring 41may be electrically connected to the gate electrode 233. A lower surfaceof the gate wiring 41 may be disposed in contact with an upper surfaceof the gate electrode 233.

The source electrode 71 may be electrically connected to the sourcecontact portion 31. The source electrode 71 may be disposed in contactwith an upper surface of the source contact portion 31. For example, thesource electrode 71 may be electrically connected to a first region ofthe channel layer 260 via the source contact portion 31. The drainelectrode 72 may be electrically connected to the drain contact portion32. The drain electrode 72 may be disposed in contact with an uppersurface of the drain contact portion 32. For example, the drainelectrode 72 may be electrically connected to a second region of thechannel layer 260 via the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may beprovided with a material in ohmic contact with the channel layer 260.The source contact portion 31 and the drain contact portion 32 maycomprise a material in ohmic contact with the second nitridesemiconductor layer 262. For example, the source contact portion 31 andthe drain contact portion 32 may comprise a single layer or multiplelayers comprising at least one material selected from the groupconsisting of aluminum (Al), an aluminum alloy (Al alloy), tungsten (W),copper (Cu), a copper alloy (Cu alloy), molybdenum (Mo), silver (Ag), asilver alloy (Ag alloy), gold (Au), a gold alloy (Au alloy), chromium(Cr), titanium (Ti), a titanium alloy (Ti alloy), molybdenum tungsten(MoW), molybdenum titanium (MoTi), and copper/molybdenum titanium(Cu/MoTi). The source contact portion 31 and the drain contact portion32 may be provided in a thickness of 0.1 to 1 μm as an example. Sincethe source contact portion 31 and the drain contact portion 32 do notneed to serve to spread a current as a layer for contacting with thechannel layer 260, the source contact portion 31 and the drain contactportion 32 may be provided in a thickness of 1 μm or less.

The gate electrode 233 may be provided as a material in Schottky contactwith the channel layer 260. The gate electrode 233 may be provided witha material which is in a Schottky contact with the second nitridesemiconductor layer 262. The gate electrode 233 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of nickel (Ni), platinum (Pt), gold (Au), andpalladium (Pd), or an alloy thereof. For example, the Schottky contactmay be implemented by plasma treatment of the channel layer 260. In theplasma treatment, for example, fluorine (F) ion treatment may beapplied. Accordingly, the thin film transistor 230 according to anembodiment may be provided with a threshold voltage by the Schottkycontact and may have a normally off characteristic. When a voltage equalto or higher than the threshold voltage is applied to the gate electrode233, a channel formed under the gate electrode 233 is turned on to allowa current to flow the channel layer 260.

Meanwhile, according to the channel layer 260 according to anembodiment, the first nitride semiconductor layer 261 may comprise a GaNsemiconductor layer, and the second nitride semiconductor layer 262 maycomprise an AlGaN semiconductor layer. As a thickness of the secondnitride semiconductor layer 262 is larger, the two-dimensional electrongas (2 DEG) is well formed, and thus it is difficult to make a normallyoff characteristic. In addition, when the thickness of the secondnitride semiconductor layer 262 is too thin, there is a problem thatgate leakage may be increased. Accordingly, it may be desirable that thethickness of the second nitride semiconductor layer 262 disposed underthe recessed region is provided in a thickness of 2 to 10 nm. Inaddition, as a method for reducing gate leakage, an insulator may bedisposed between the gate electrode 233 and the second nitridesemiconductor layer 262 to be provided in aMetal-Insulator-Semiconductor (MIS) structure. For example, the secondnitride semiconductor layer 262 in a region where the recess is notformed may be provided in a thickness of 15 to 25 nm. In addition, therecess may be provided in a width of 1.5 to 2.5 μm as an example.

The gate wiring 41 may comprise a single layer or multiple layerscomprising at least one material selected from the group consisting ofaluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu),a copper alloy (Cu alloy), molybdenum (Mo), silver (Ag), a silver alloy(Ag alloy), gold (Au), a gold alloy (Au alloy), chromium (Cr), titanium(Ti), a titanium alloy (Ti alloy), molybdenum tungsten (MoW), molybdenumtitanium (MoTi), and copper/molybdenum titanium (Cu/MoTi). The gatewiring 41 may be provided in a thickness of 0.1 to 3 μm as an example.Since the gate wiring 41 serves to sequentially apply a voltage to aplurality of transistors, the gate wiring 41 may be provided to bethicker than a thickness of the gate electrode 33.

The source electrode 71 and the drain electrode 72 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of aluminum (Al), an aluminum alloy (Al alloy),tungsten (W), copper (Cu), a copper alloy (Cu alloy), molybdenum (Mo),silver (Ag), a silver alloy (Ag alloy), gold (Au), a gold alloy (Aualloy), chromium (Cr), titanium (Ti), a titanium alloy (Ti alloy),molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The source electrode 71 and thedrain electrode 72 may be provided in a thickness of 0.1 to 3 μm as anexample. Since the source electrode 71 serves to sequentially apply avoltage to the plurality of transistors, the source electrode 71 may beprovided to be thicker than a thickness of the source contact portion31. Also, the drain electrode 72 may be provided to be thicker than athickness of the drain contact portion 32.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 21 disposed on the channel layer 260.The first passivation film 21 may be disposed on the second nitridesemiconductor layer 262. A lower surface of the first passivation film21 may be disposed in contact with an upper surface of the secondnitride semiconductor layer 262.

According to an embodiment, the source contact portion 31 may bedisposed to pass through the first passivation film 21. The sourcecontact portion 31 may be disposed to be surrounded by the firstpassivation film 21. The source contact portion 31 may be disposed topass through the first passivation film 21 and provided in contact withthe first region of the channel layer 260. The drain contact portion 32may be disposed to pass through the first passivation film 21. The draincontact portion 32 may be disposed to be surrounded by the firstpassivation film 21. The drain contact portion 32 may be disposed topass through the first passivation film 21 and provided in contact withthe second region of the channel layer 260.

The first passivation film 21 may be provided with an insulatingmaterial. The first passivation film 21 may comprise a single layer ormultiple layers comprising at least one of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55 and the first passivation film 21. The gateelectrode 233 may be disposed to pass through at least one of the firstpassivation film 21 and the second passivation film 22. For example, thegate electrode 233 may be disposed to pass through the first passivationfilm 21 and the second passivation film 22. The gate electrode 233 maypass through at least one of the first passivation film 21 and thesecond passivation film 22 and be disposed in contact with the channellayer 260. For example, the gate electrode 233 may pass through thefirst passivation film 21 and the second passivation film 22 and bedisposed in contact with the channel layer 260. The gate wiring 41 maybe disposed on the second passivation film 22 and be electricallyconnected to the gate electrode 233.

The second passivation film 22 may be provided with an insulatingmaterial. The second passivation film 22 may comprise a single layer ormultiple layers including at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide including Al₂O₃, and anorganic insulating material as an example.

According to an embodiment, a third passivation film 23 may be disposedon the second passivation film 22. The third passivation film 23 may bedisposed on the second passivation film 22 and the gate wiring 41. Thegate wiring 41 may be disposed in contact with the gate electrode 233thereon and provided to be surrounded by the third passivation film 23.

The source electrode 71 may pass through the second passivation film 22and the third passivation film 23 and be electrically connected to thesource contact portion 31. The source electrode 71 may comprise a firstregion disposed on the third passivation film 23. The source electrode71 may comprise a second region passing through the third passivationfilm 23 and the second passivation film 22. The drain electrode 72 maypass through the second passivation film 22 and the third passivationfilm 23 and be electrically connected to the drain contact portion 32.The drain electrode 72 may comprise a first region disposed on the thirdpassivation film 23. The drain electrode 72 may comprise a second regionpassing through the third passivation film 23 and the second passivationfilm 22.

The third passivation film 23 may comprise an insulating material. Thethird passivation film 23 may comprise a single layer or multiple layerscomprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 24 disposed on the third passivationfilm 23. The fourth passivation film 24 may be disposed on the sourceelectrode 71 and the drain electrode 72. The fourth passivation film 24may comprise a contact hole H3 provided on the drain electrode 72.

The fourth passivation film 24 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

According to an embodiment, the pixel electrode 80 may be disposed onthe fourth passivation film 24. The pixel electrode 80 may beelectrically connected to the drain electrode 72 via the contact hole H3provided in the fourth passivation film 24. A lower surface of the pixelelectrode 80 may be disposed in contact with an upper surface of thedrain electrode 72.

The pixel electrode 80 may be provided with a transparent conductivematerial. The pixel electrode 80 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 80 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The thin film transistor substrate according to an embodiment maycomprise a black matrix 40 between the substrate 55 and the channellayer 260. A width of the channel layer 260 may be provided to be equalto a width of the black matrix 40. The black matrix 40 may be providedin a single layer or multiple layers including at least one materialselected from among a Si-based material, a Ga-based material, anAl-based material, and an organic material. The black matrix 40 mayblock light incident on the thin film transistor 230. Accordingly, it ispossible to prevent the thin film transistor 230 from deteriorating dueto a photo current or the like.

According to an embodiment, the bonding layer 50 may be disposed betweenthe substrate 55 and the channel layer 260. The bonding layer 50 may bedisposed between the substrate 55 and the black matrix 40. For example,the bonding layer 50 may be disposed on an entire region of thesubstrate 55.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. A common electrodemay be provided at the color filter substrate, and an arrangement of theliquid crystal layer disposed between the common electrode and the pixelelectrode provided on the thin film transistor substrate may becontrolled by a difference in voltage applied therebetween, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a vertical electric field type liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 33 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIG. 33 is anembodiment to which a thin film transistor having a structure in whichgates are disposed in a recessed region of a channel layer is applied,and description of contents overlapping with those described withreference to FIGS. 1 to 32 may be omitted.

The thin film transistor substrate described with reference to FIG. 32may be applied to a vertical electric field type liquid crystal displaypanel. Meanwhile, the thin film transistor substrate described withreference to FIG. 33 may be applied to a horizontal electric field typeliquid crystal display panel.

As shown in FIG. 33, the thin film transistor substrate according to anembodiment may comprise a pixel electrode 81, a common electrode 85, anda fifth passivation film 25.

The common electrode 85 may be disposed on a fourth passivation film 24.The fifth passivation film 25 may be disposed on the fourth passivationfilm 24. The fifth passivation film 25 may be disposed on the commonelectrode 85 and the fourth passivation film 24. The common electrode 85may be disposed between the fourth passivation film 24 and the fifthpassivation film 25. In addition, the fifth passivation film 25 may beprovided on a drain electrode 72 exposed through the fourth passivationfilm 24. The pixel electrode 81 may be disposed on the fifth passivationfilm 25. A partial region of the pixel electrode 81 may be electricallyconnected to the drain electrode 72 through a fourth contact hole H4provided in the fifth passivation film 25. A partial region of the pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 through the fourth contact hole H4. The pixelelectrode 81 may be disposed in contact with the upper surface of thedrain electrode 72 by passing through the fourth passivation film 24 andthe fifth passivation film 25. A partial region of the pixel electrode81 and a partial region of the common electrode 85 may be overlappedwith each other in a vertical direction.

The thin film transistor substrate according to an embodiment maycomprise a plurality of thin film transistors 230 disposed in a regionin which a gate wiring 41 and a data wiring 73 intersect with eachother. The pixel electrode 81 may be disposed at a region that isdefined by the gate wiring 41 and the data wiring 73. The pixelelectrode 81 may comprise a portion extending in a finger shape. Apartial region of the pixel electrode 81 may be disposed and overlappedwith the gate wiring 41.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 81 may be provided with a transparent conductivematerial. The pixel electrode 81 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 81 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The fifth passivation film 25 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment may bebonded to a color filter substrate to provide a liquid crystal displaypanel. A liquid crystal layer may be provided between the thin filmtransistor substrate and the color filter substrate. In the thin filmtransistor substrate according to an embodiment, an arrangement of theliquid crystal layer may be adjusted by a difference in voltage appliedbetween the common electrode 85 and the pixel electrode 81, and a lighttransmission amount of a corresponding pixel may be controlled. Theliquid crystal display panel having such a structure may be referred toas a horizontal electric field type liquid crystal display panel, atransverse electric field type liquid crystal display panel, or an InPlane Switching (IPS) liquid crystal display panel. Since the liquidcrystal display panel itself has no light source, a display device maybe implemented by providing a light unit that supplies light to theliquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 34 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. The thin film transistor substrate shown in FIG. 34 is anembodiment to which a thin film transistor having a structure in whichgates are disposed in a recessed region of a channel layer is applied,and description of contents overlapping with those described withreference to FIGS. 1 to 33 may be omitted.

The thin film transistor substrate according to an embodiment maycomprise a pixel electrode 82, a common electrode 85, a metal layer 90,a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on a fourth passivation film 24.The pixel electrode 82 may be disposed on a fifth passivation film 25.The pixel electrode 82 may be electrically connected to a drainelectrode 72. The metal layer 90 may be provided between the pixelelectrode 82 and the drain electrode 72. The metal layer 90 may bedisposed in contact with the drain electrode 72 exposed through thefourth passivation film 24. A partial region of the pixel electrode 82may be electrically connected to the drain electrode 72 through themetal layer 90 through a fifth contact hole H5 provided in the fifthpassivation film 25.

According to an embodiment, the touch panel upper electrode 92 may beprovided on the fifth passivation film 25 and the touch panel lowerelectrode 91 may be disposed below the touch panel upper electrode 92.The touch panel lower electrode 91 may be disposed on the fourthpassivation film 24 and may be electrically connected to the commonelectrode 85. The touch panel lower electrode 91 may be disposed betweenthe common electrode 85 and the fifth passivation film 25. The touchpanel upper electrode 92 may be disposed to be overlapped with the touchpanel lower electrode 91 in a vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode91 may form an in-cell touch panel provided in the display panel.Accordingly, the thin film transistor substrate according to anembodiment may detect a contact of the display panel from outside byusing the in-cell touch panel.

The common electrode 85 may be provided with a transparent conductivematerial. The common electrode 85 may be provided with, for example, atransparent conductive oxide film. The common electrode 85 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The pixel electrode 82 may be provided with a transparent conductivematerial. The pixel electrode 82 may be provided with, for example, atransparent conductive oxide film. The pixel electrode 82 may compriseat least one material selected from among indium tin oxide (ITO), indiumzinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide(AGZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO),indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO),antimony tin oxide (ATO), gallium zinc oxide (GZO), and IZO nitride(IZON).

The touch panel lower electrode 91 and the touch panel upper electrode92 may be formed of a transparent conductive material. The pixelelectrode 82 may be provided with, for example, a transparent conductiveoxide film. The pixel electrode 82 may comprise at least one materialselected from among indium tin oxide (ITO), indium zinc oxide (IZO),aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indiumzinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium galliumzinc oxide (IGZO), indium gallium tin oxide (IGTO), antimony tin oxide(ATO), gallium zinc oxide (GZO), and IZO nitride (IZON).

The in-cell touch panel-integrated thin film transistor substrateaccording to an embodiment may be bonded to a color filter substrate toprovide a liquid crystal display panel. A liquid crystal layer may beprovided between the in-cell touch panel-integrated thin film transistorsubstrate and the color filter substrate. In the in-cell touchpanel-integrated thin film transistor substrate according to anembodiment, an arrangement of the liquid crystal layer may be adjustedby a difference in voltage applied between the common electrode 85 andthe pixel electrode 82, and a light transmission amount of acorresponding pixel may be controlled. The in-cell touchpanel-integrated liquid crystal display panel having such a structuremay be referred to as a horizontal electric field type liquid crystaldisplay panel, a transverse electric field type liquid crystal displaypanel, or an In Plane Switching (IPS) liquid crystal display panel.Since the in-cell touch panel-integrated liquid crystal display panelitself has no light source, a display device may be implemented byproviding a light unit that supplies light to the in-cell touchpanel-integrated liquid crystal display panel.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 35 to 37 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 35 to 37, in the description of the thinfilm transistor substrate according to an embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to34 may be omitted. An embodiment shown in FIGS. 35 to 37 differs fromthat of each of FIGS. 32, 33, and 34 in the bonding layer structure.

As shown in FIGS. 35 to 37, a bonding layer 53 may be provided on thesubstrate 55. The bonding layer 53 may be disposed between the substrate55 and the black matrix 40. For example, a width of the bonding layer 53may be provided to be equal to a width of the black matrix 40. Forexample, the width of the bonding layer 53 may be provided to be equalto a width of the channel layer 260.

According to an embodiment, a second passivation film 22 may be disposedon the substrate 55. A lower surface of the second passivation film 22may be disposed in contact with an upper surface of the substrate 55. Ina region where the bonding layer 50 is not provided, the secondpassivation film 22 may be disposed in direct contact with the substrate55.

As described above, according to the embodiment shown in FIGS. 35 to 37,as compared with the embodiment shown in FIGS. 32, 33, and 34, since thesecond passivation film 22 and the substrate 55 may be disposed indirect contact with each other, a layer provided between the secondpassivation film 22 and the substrate 55 (for example, an illustratedbonding layer in FIGS. 32, 33, and 34) may be eliminated. Accordingly,according to the embodiment, since an interface between differentmaterial layers is reduced on a light path where light travels, lightloss due to reflection/refraction at the interface may be reduced.

The bonding layer 53 according to an embodiment may comprise at leastone of a reflective layer, a metal bonding layer, an organic bondinglayer, and an insulating layer as an example. The reflective layer maybe disposed on the substrate 55, the metal bonding layer may be disposedon the reflective layer, and the insulating layer may be disposed on themetal bonding layer. For example, the bonding layer 53 may comprise atleast one of the metal bonding layer and the organic bonding layer, andthe reflective layer and the insulating layer may be comprisedselectively.

The insulating layer may complement the leakage characteristics of thechannel layer 260. For example, the insulating layer may comprise asingle layer or multiple layers including at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide includingAl₂O₃, and an organic insulating material as an example.

The metal bonding layer or the organic bonding layer may be provided forbonding with the substrate 55 disposed thereunder. For example, themetal bonding layer may comprise at least one material selected from thegroup consisting of gold (Au), tin (Sn), indium (In), nickel (Ni),silver (Ag), and copper (Cu), or an alloy thereof. For example, theorganic bonding layer may comprise at least one material selected fromthe group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, andthe like.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

Meanwhile, according to an embodiment, for example, when the bondinglayer 53 comprises the metal bonding layer and the reflective layer, theblack matrix 40 may be omitted.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIGS. 38 to 40 are views illustrating still another example of a thinfilm transistor substrate according to an embodiment of the presentinvention. Referring to FIGS. 38 to 40, in the description of the thinfilm transistor substrate according to the embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to37 may be omitted. An embodiment shown in FIGS. 38 to 40 differs fromthat of each of FIGS. 32, 33, and 34 in that a transfer process is notapplied and a thin film transistor is provided on a growth substrate.

As shown in FIGS. 38 to 40, the thin film transistor substrate accordingto the embodiment may comprise a growth substrate 10 as a substrateinstead of a support substrate used in the transfer process. Forexample, the growth substrate 10 may comprise at least one of groupconsisting of sapphire, SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

A black matrix 45 may be disposed on the growth substrate 10. The blackmatrix 45 is disposed on the growth substrate 10 and may prevent lightfrom being incident on the channel layer 260. The black matrix 45 may beprovided with a material that absorbs or reflects visible rays as anexample. Thus, according to the embodiment, light is incident on thechannel layer 260 and it is possible to prevent a thin film transistor230 from being deteriorated due to a photo current or the like. Forexample, the black matrix 45 may be provided in a single layer ormultiple layers including at least one material selected from among aSi-based material, a Ga-based material, an Al-based material, and anorganic material. The black matrix 45 may selectively comprise amaterial such as Si, GaAs, or the like.

According to an embodiment, a buffer layer 47 may be provided on theblack matrix 45. The buffer layer 47 may be provided between the blackmatrix 45 and the channel layer 260. The buffer layer 47 may help agrowth of a nitride semiconductor layer constituting the channel layer260. For example, the buffer layer 47 may comprise a single layer ormultiple layers including at least one material selected from the groupconsisting of AlN, AlInN, and AlGaN.

For example, a width of the black matrix 45 may be provided to be equalto a width of the buffer layer 47. For example, the width of the blackmatrix 45 may be provided to be equal to a width of the channel layer260. The width of the buffer layer 47 may be provided to be equal to thewidth of the channel layer 260.

According to an embodiment, the second passivation film 22 may bedisposed on the growth substrate 10. A lower surface of the secondpassivation film 22 may be disposed in contact with an upper surface ofthe growth substrate 10. In a region where the black matrix 45 is notprovided, the second passivation film 22 may be disposed in directcontact with the growth substrate 10.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 41 is a block diagram illustrating an example of a display devicecomprising a thin film transistor substrate according to an embodimentof the present invention.

The display device according to an embodiment may comprise a displaypanel 1100, a light unit 1200, and a panel driver 1300 as shown in FIG.41.

The display panel 1100 may comprise any one of the thin film transistorsubstrates described with reference to FIGS. 1 to 40 and a color filtersubstrate disposed on the thin film transistor substrate. The displaypanel 1100 may comprise a liquid crystal layer disposed between the thinfilm transistor substrate and the color filter substrate.

The light unit 1200 may be disposed under the display panel 1100 and maysupply light to the display panel 1100. The panel driver 1300 mayprovide a driving signal to the display panel 1100. The panel driver1300 may control the light transmittance of a plurality of pixelsprovided in the display panel 1100 and may display an image on thedisplay panel 1100 by using light provided from the light unit 1200.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate. Meanwhile,as explained above, according to an embodiment, a thin film transistorand a pixel electrode are provided on a growth substrate and a thin filmtransistor substrate having an excellent electron mobility may beprovided.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 42 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. FIG. 43 is a cross-sectional view taken along line D-D of thethin film transistor substrate shown in FIG. 42, and FIG. 44 is across-sectional view taken along line E-E of the thin film transistorsubstrate shown in FIG. 42.

Embodiments described with reference to FIGS. 1 to 41 relate to a thinfilm transistor substrate capable of being applied to a liquid crystaldisplay device, and the thin film transistor substrate described withreference to FIGS. 42 to 44 may be applied to an organic light-emittingdisplay device.

The thin film transistor substrate according to an embodiment maycomprise a switching thin film transistor 330 and a driving thin filmtransistor 430. The switching thin film transistor 330 may receive asignal from a gate line 341 and a data line 373 and may provide a gatesignal and a data signal to a corresponding pixel. The switching thinfilm transistor 330 may comprise a first gate electrode 333, a firstsource electrode 371, and a first drain electrode 372. The driving thinfilm transistor 430 may comprise a second gate electrode 433, a secondsource electrode 471, and a second drain electrode 472. The second gateelectrode 433 of the driving thin film transistor 430 may beelectrically connected to the first drain electrode 372 of the switchingthin film transistor 330. The second source electrode 471 of the drivingthin film transistor 430 may be connected to a driving power supply line(Vdd) 474. Operations of the switching thin film transistor 330 and thedriving thin film transistor 430 will be described later with referenceto FIG. 45.

As shown in FIGS. 42 to 44, the thin film transistor substrate accordingto an embodiment of the present invention may comprise a substrate 355,the switching thin film transistor 330 disposed on the substrate 355,the driving thin film transistor 430, and a light-emitting layer 488electrically connected to the driving thin film transistor 430.

The switching thin film transistor 330 according to an embodiment maycomprise a first depletion forming layer 315, a first gate electrode333, a first channel layer 360, a first source electrode 371, and afirst drain electrode 372. The first source electrode 371 may beelectrically connected to a first region of the first channel layer 360.The first source electrode 371 may be electrically connected to an uppersurface of the first channel layer 360. The first drain electrode 372may be electrically connected to a second region of the first channellayer 360. The first drain electrode 372 may be electrically connectedto the upper surface of the first channel layer 360. The first gateelectrode 333 may be disposed on the first channel layer 360. The firstdepletion forming layer 315 may be disposed on between the first regionand the second region of the first channel layer 360. The firstdepletion forming layer 315 may be disposed between the first channellayer 360 and the first gate electrode 333.

The driving thin film transistor 430 according to an embodiment maycomprise a second depletion forming layer 415, a second gate electrode433, a second channel layer 460, a second source electrode 471, and asecond drain electrode 472. The second source electrode 471 may beelectrically connected to a first region of the second channel layer460. The second source electrode 471 may be electrically connected to anupper surface of the second channel layer 460. The second drainelectrode 472 may be electrically connected to a second region of thesecond channel layer 460. The second drain electrode 472 may beelectrically connected to the upper surface of the second channel layer460. The second gate electrode 433 may be disposed on the second channellayer 460. The second depletion forming layer 415 may be disposed onbetween the first region and the second region of the second channellayer 460. The second depletion forming layer 415 may be disposedbetween the second channel layer 460 and the second gate electrode 433.

The structures of the switching thin film transistor 330 and the drivingthin film transistor 430 may be similar to each other, and in thedescription of the driving thin film transistor 430, description ofcontents overlapping with those described with reference to theswitching thin film transistor 330 may be omitted.

The first channel layer 360 and the second channel layer 460 may beprovided with, for example, a Group III-V compound semiconductor. Forexample, the first channel layer 360 and the second channel layer 460may be provided with a semiconductor material having an empiricalformula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The firstchannel layer 360 and the second channel layer 460 may comprise a singlelayer or multiple layers selected from, for example, GaN, AlN, AlGaN,InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and so on.The first channel layer 360 and the second channel layer 460 may beformed of different materials.

The first channel layer 360 and the second channel layer 460 may eachcomprise first nitride semiconductor layers 361 and 461 and secondnitride semiconductor layers 362 and 462. The first nitridesemiconductor layers 361 and 461 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layers 362 and 462 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).

According to the first channel layer 360 and the second channel layer460 according to an embodiment, the first nitride semiconductor layers361 and 461 may comprise a GaN semiconductor layer, and the secondnitride semiconductor layers 362 and 462 may comprise an AlGaNsemiconductor layer. The second nitride semiconductor layer 362 of thefirst channel layer 360 may be disposed between the first nitridesemiconductor layer 361 and the first depletion forming layer 315. Thesecond nitride semiconductor layer 462 of the second channel layer 460may be disposed between the first nitride semiconductor layer 461 andthe second depletion forming layer 415.

The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided with, for example, a group III-V compoundsemiconductor. For example, the first depletion forming layer 315 andthe second depletion forming layer 415 may be provided with asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The first depletionforming layer 315 and the second depletion forming layer 415 maycomprise a single layer or multiple layers selected from, for example,GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP,AlGaInP and so on. The first depletion forming layer 315 and the seconddepletion forming layer 415 may comprise a nitride semiconductor layerdoped with a p-type dopant. For example, the first depletion forminglayer 315 and the second depletion forming layer 415 may comprise a GaNsemiconductor layer doped with a p-type dopant or an AlGaN semiconductorlayer doped with a p-type dopant. The first depletion forming layer 315and the second depletion forming layer 415 may comprise a single layeror multiple layers provided with, for example, a semiconductor materialhaving an empirical formula of p-Al_(x)Ga_(1-x)N (0≥x≥0.3).

The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided in a thickness of 2 to 300 nm as an example.The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided in a thickness of at least 2 nm in order toprovide a depletion region at two-dimensional electron gas (2 DEG)provided at the first channel layer 360 and the second channel layer460. In addition, the first depletion forming layer 315 and the seconddepletion forming layer 415 may be provided in a thickness of 30 nm ormore in consideration of a thickness deviation according to amanufacturing process. In addition, the first depletion forming layer315 and the second depletion forming layer 415 may be provided in athickness of 200 nm or less in consideration of a thickness deviationaccording to a manufacturing process. The first depletion forming layer315 and the second depletion forming layer 415 may be provided in athickness of 50 to 100 nm as an example.

The first depletion forming layer 315 and the second depletion forminglayer 415 may comprise different materials. Substances added to thefirst depletion forming layer 315 and the second depletion forming layer415, and addition amounts of the added substances may be different fromeach other.

The first depletion forming layer 315 and the second depletion forminglayer 415 may serve to form a depletion region in a two-dimensionalelectron gas (2 DEG) provided in the first channel layer 360 and thesecond channel layer 460. The energy bandgap of a portion of the secondnitride semiconductor layer 362 positioned thereunder may be increasedby the first depletion forming layer 315. As a result, the depletionregion of the 2 DEG may be provided at a portion of the first channellayer 360 corresponding to the first depletion forming layer 315.Therefore, a region corresponding to the position in which the firstdepletion forming layer 315 is disposed in the 2 DEG provided at thefirst channel layer 360 may be cut off. A region in which the 2 DEG iscut off at the first channel layer 360 may be referred to as a cut-offregion, and, for example, a cut-off region may be formed at the secondnitride semiconductor layer 362. The switching thin film transistor 330may have a normally-off characteristic due to such a cut-off region.When a voltage equal to or higher than a threshold voltage is applied tothe first gate electrode 333, the 2 DEG is generated at the cut-offregion and the switching thin film transistor 330 is turned on. When achannel formed at a lower portion of the first gate electrode 333 isturned on, a current may flow via the 2 DEG formed at the first channellayer 360. Accordingly, the current flow from the first region to thesecond region of the first channel layer 360 may be controlled accordingto a voltage applied to the first gate electrode 333. The seconddepletion forming layer 415 may perform a function similar to that ofthe first depletion forming layer 315.

The substrate 355 may comprise a transparent substrate. The substrate355 may be provided with a transparent substrate having a thickness of0.1 mm to 3 mm as an example. In addition, the thickness of thesubstrate 355 may be changed according to application and size of anapplied display device and may be selected within a thickness range of0.4 to 1.1 mm. For example, the substrate 355 may be provided in athickness of 0.6 to 0.8 mm. The substrate 355 may comprise at least onematerial selected from materials including silicon, glass, polyimide,and plastic. The substrate 355 may comprise a flexible substrate.

The substrate 355 is a substrate to be used in a transfer process, andserves to support the switching thin film transistor 330 and the drivingthin film transistor 430. In addition, the thin film transistorsubstrate according to an embodiment may comprise a bonding layer 350provided between the substrate 355 and the switching thin filmtransistor 330. The bonding layer 350 may be disposed between thesubstrate 355 and the driving thin film transistor 430.

The bonding layer 350 may comprise an organic material. The bondinglayer 350 may be provided with a transparent material. The bonding layer350 may be provided with, for example, a material having a transmittanceof 70% or more. The bonding layer 350 may comprise an organic insulatingmaterial. The bonding layer 350 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 350 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer350 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer350 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The switching thin film transistor 330 according to an embodiment maycomprise a first source contact portion 331 disposed on the first regionof the first channel layer 360 and a first drain contact portion 332disposed on the second region of the first channel layer 360. The firstsource contact portion 331 may be disposed in contact with the firstregion of the first channel layer 360. The first drain contact portion332 may be disposed in contact with the second region of the firstchannel layer 360.

A switching thin film transistor 330 according to an embodiment maycomprise a first gate wiring 341 disposed on the first gate electrode333. The first gate wiring 341 may be electrically connected to thefirst gate electrode 333. A lower surface of the first gate wiring 341may be disposed in contact with an upper surface of the first gateelectrode 333.

The first source electrode 371 may be electrically connected to thefirst source contact portion 331. The first source electrode 371 may bedisposed in contact with an upper surface of the first source contactportion 331. For example, the first source electrode 371 may beelectrically connected to a first region of the first channel layer 360via the first source contact portion 331. The first drain electrode 372may be electrically connected to the first drain contact portion 332.The first drain electrode 372 may be disposed in contact with an uppersurface of the first drain contact portion 332. For example, the firstdrain electrode 372 may be electrically connected to a second region ofthe first channel layer 360 via the first drain contact portion 332.

The driving thin film transistor 430 according to an embodiment maycomprise a second source contact portion 431 disposed on the firstregion of the second channel layer 460 and a second drain contactportion 432 disposed on the second region of the second channel layer460. The second source contact portion 431 may be disposed in contactwith the first region of the second channel layer 460. The second draincontact portion 432 may be disposed in contact with the second region ofthe second channel layer 460.

A driving thin film transistor 430 according to an embodiment maycomprise a second gate wiring 441 disposed on the second gate electrode433. The second gate wiring 441 may be electrically connected to thesecond gate electrode 433. A lower surface of the second gate wiring 441may be disposed in contact with an upper surface of the second gateelectrode 433.

The second source electrode 471 may be electrically connected to thesecond source contact portion 431. The second source electrode 471 maybe disposed in contact with an upper surface of the second sourcecontact portion 431. For example, the second source electrode 471 may beelectrically connected to a first region of the second channel layer 460via the second source contact portion 431. The second drain electrode472 may be electrically connected to the second drain contact portion432. The second drain electrode 472 may be disposed in contact with anupper surface of the second drain contact portion 432. For example, thesecond drain electrode 472 may be electrically connected to a secondregion of the second channel layer 460 via the second drain contactportion 432.

The first source contact portion 331 and the first drain contact portion332 may be provided with a material in ohmic contact with the firstchannel layer 360. The first source contact portion 331 and the firstdrain contact portion 332 may comprise a material in ohmic contact withthe second nitride semiconductor layer 362. The second source contactportion 431 and the second drain contact portion 432 may be providedwith a material in ohmic contact with the second channel layer 460. Thesecond source contact portion 431 and the second drain contact portion432 may comprise a material in ohmic contact with the second nitridesemiconductor layer 462. For example, the first source contact portion331, the first drain contact portion 332, the second source contactportion 431, and the second drain contact portion 432 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first source contact portion331, the first drain contact portion 332, the second source contactportion 431, and the second drain contact portion 432 may be provided ina thickness of 0.1 to 1 μm as an example. The first source contactportion 331, the first drain contact portion 332, the second sourcecontact portion 431, and the second drain contact portion 432 do notneed to serve to spread a current as a layer for contacting with thefirst channel layer 360 and the second channel layer 460. Accordingly,the first source contact portion 331, the first drain contact portion332, the second source contact portion 431, and the second drain contactportion 432 may be provided in a thickness of 1 μm or less.

The first gate electrode 333 may be provided with a material in ohmiccontact with the first depletion forming layer 315. The second gateelectrode 433 may be provided with a material in ohmic contact with thesecond depletion forming layer 415. For example, the first gateelectrode 333 and the second gate electrode 433 may be provided with amaterial in ohmic contact with a p-type nitride layer. The first gateelectrode 333 and the second gate electrode 433 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of tungsten (W), tungsten silicon (WSi2), titaniumnitride (TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd),nickel (Ni), and platinum (Pt). The first gate electrode 333 and thesecond gate electrode 433 may be provided in a thickness of 0.1 to 1 μmas an example. Since the first gate electrode 335 and the second gateelectrode 433 does not need to serve to spread a current as a layer forcontacting with the first depletion forming layer 315 and the seconddepletion forming layer 415, the first gate electrode 335 and the secondgate electrode 435 may be provided in a thickness of 1 μm or less.

The first gate wiring 341 and the second gate wiring 441 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first gate wiring 341 and thesecond gate wiring 441 may be provided in a thickness of 0.1 to 3 μm asan example. Since the first gate wiring 341 and the second gate wiring441 serves to sequentially apply a voltage to a plurality oftransistors, the first gate wiring 341 and the second gate wiring 441may be provided to be thicker than a thickness of the first gateelectrode 333 and the second gate electrode 433.

The first source electrode 371, the first drain electrode 372, thesecond source electrode 471, and the second drain electrode 472 maycomprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of aluminum (Al), analuminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy (Cualloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold(Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), a titaniumalloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi),and copper/molybdenum titanium (Cu/MoTi). The first source electrode371, the first drain electrode 372, the second source electrode 471, andthe second drain electrode 472 may be provided in a thickness of 0.1 to3 μm as an example. Since the first source electrode 371 and the secondsource electrode 471 serve to sequentially apply a voltage to theplurality of transistors, the first source electrode 371 and the secondsource electrode 471 may be provided to be thicker than a thickness ofthe first source contact portion 331 and the second source contactportion 431. Also, the first drain electrode 372 and the second drainelectrode 472 may be provided to be thicker than a thickness of thefirst drain contact portion 332 and the second drain contact portion432.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 321 and 421 disposed on the firstchannel layer 360 and the second channel layer 460. The firstpassivation film 321 and 421 may be disposed on the second nitridesemiconductor layer 362 of the first channel layer 360 and the secondnitride semiconductor layer 462 of the second channel layer 460. A lowersurface of the first passivation film 321 and 421 may be disposed incontact with an upper surface of the second nitride semiconductor layer362 of the first channel layer 360 and the second nitride semiconductorlayer 462 of the second channel layer 460. The first passivation film321 and 421 may be disposed on the first depletion forming layer 315 andthe second depletion forming layer 415. The first passivation film 321and 421 may be disposed at a side surface of the first depletion forminglayer 315 and the second depletion forming layer 415. The firstpassivation film 321 and 421 may be disposed so as to surround the sidesurface of the first depletion forming layer 315 and the seconddepletion forming layer 415.

According to an embodiment, the first source contact portion 331 may bedisposed to pass through the first passivation film 321. The firstsource contact portion 331 may be disposed to be surrounded by the firstpassivation film 321. The first source contact portion 331 may bedisposed to pass through the first passivation film 321 and provided incontact with the first region of the first channel layer 360. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321. The first drain contact portion 332 may bedisposed to be surrounded by the first passivation film 321. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321 and provided in contact with the second region ofthe first channel layer 360.

According to an embodiment, the second source contact portion 431 may bedisposed to pass through the first passivation film 421. The secondsource contact portion 431 may be disposed to be surrounded by the firstpassivation film 421. The second source contact portion 431 may bedisposed to pass through the first passivation film 421 and provided incontact with the first region of the second channel layer 460. Thesecond drain contact portion 432 may be disposed to pass through thefirst passivation film 421. The second drain contact portion 432 may bedisposed to be surrounded by the first passivation film 421. The seconddrain contact portion 432 may be disposed to pass through the firstpassivation film 421 and provided in contact with the second region ofthe second channel layer 460.

The first passivation film 321 and 421 may be provided with aninsulating material. The first passivation film 321 and 421 may comprisea single layer or multiple layers comprising at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide comprisingAl₂O₃, and an organic insulating material as an example.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355 and the first passivation film 321 and421. The first gate electrode 333 may be disposed to pass through atleast one of the first passivation film 321 and the second passivationfilm 322. For example, the first gate electrode 333 may be disposed topass through the first passivation film 321 and the second passivationfilm 322. The first gate electrode 333 may pass through at least one ofthe first passivation film 321 and the second passivation film 322 andbe disposed in contact with the first depletion forming layer 315. Forexample, the first gate electrode 333 may pass through the firstpassivation film 321 and the second passivation film 322 and be disposedin contact with the first depletion forming layer 315. The first gatewiring 341 may be disposed on the second passivation film 322 and beelectrically connected to the first gate electrode 333. The second gateelectrode 433 may be disposed to pass through at least one of the firstpassivation film 321 and the second passivation film 322. For example,the second gate electrode 433 may be disposed to pass through the firstpassivation film 321 and the second passivation film 322. The secondgate electrode 433 may pass through at least one of the firstpassivation film 321 and the second passivation film 322 and be disposedin contact with the second depletion forming layer 415. For example, thesecond gate electrode 433 may pass through the first passivation film321 and the second passivation film 322 and be disposed in contact withthe second depletion forming layer 415. The second gate wiring 441 maybe disposed on the second passivation film 322 and be electricallyconnected to the second gate electrode 433.

The second passivation film 322 may be provided with an insulatingmaterial. The second passivation film 322 may comprise a single layer ormultiple layers including at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide including Al₂O₃, and anorganic insulating material as an example.

According to an embodiment, a third passivation film 323 may be disposedon the second passivation film 322. The third passivation film 323 maybe disposed on the second passivation film 322, the first gate wiring341, and the second gate wiring 342. The first gate wiring 341 may bedisposed in contact with the first gate electrode 333 thereon andprovided to be surrounded by the third passivation film 323. The secondgate wiring 441 may be disposed in contact with the second gateelectrode 433 thereon and provided to be surrounded by the thirdpassivation film 323.

The first source electrode 371 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the first source contact portion 331. The first sourceelectrode 371 may comprise a first region disposed on the thirdpassivation film 323. The first source electrode 371 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The first drain electrode 372 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the first drain contact portion332. The first drain electrode 372 may comprise a first region disposedon the third passivation film 323. The first drain electrode 372 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

The second source electrode 471 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the second source contact portion 431. The second sourceelectrode 471 may comprise a first region disposed on the thirdpassivation film 323. The second source electrode 471 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The second drain electrode 472 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the second drain contact portion432. The second drain electrode 472 may comprise a first region disposedon the third passivation film 323. The second drain electrode 472 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

According to an embodiment, a first drain-gate connecting wiring 375 maybe disposed on the third passivation film 323. The first drain-gateconnecting wiring 375 may comprise a first region disposed on the thirdpassivation film 323. The first drain-gate connecting wiring 375 maycomprise a second region passing through the third passivation film 323.The first region of the first drain-gate connecting wiring 375 may beelectrically connected to the first drain electrode 372. The firstregion of the first drain-gate connecting wiring 375 may be disposed tobe extending from the first drain electrode 372. For example, the firstdrain-gate connecting wiring 375 and the first drain electrode 372 maybe integrally formed in the same process. In addition, the firstdrain-gate connecting wiring 375 and the first drain electrode 372 maybe separately formed in different processes and electrically connectedto each other.

According to an embodiment, a second drain-gate connecting wiring 475may be disposed on the second passivation film 322. The seconddrain-gate connecting wiring 475 may be electrically connected to thefirst drain-gate connecting wiring 375. The second region of the firstdrain-gate connecting wiring 375 may be disposed in contact with thesecond drain-gate connecting wiring 475. The second drain-gateconnecting wiring 475 may be electrically connected to the second gatewiring 441. The second drain-gate connecting wiring 475 may be disposedto be extending from the second gate wiring 441. For example, the seconddrain-gate connecting wiring 475 and the second gate wiring 441 may beintegrally formed in the same process. In addition, the seconddrain-gate connecting wiring 475 and the second gate wiring 441 may beformed in separate processes and electrically connected to each other.The first drain electrode 372 may be electrically connected to thesecond gate electrode 433 via the first drain-gate connecting wiring375, the second drain-gate connecting wiring 475, and the second gatewiring 441.

As shown in FIG. 44, the second channel layer 460 and the seconddepletion forming layer 415 may be formed in the same width. When awidth of the second depletion forming layer 415 is smaller than that ofthe second channel layer 460, a leakage current may be generated. Inother words, the length of the second channel layer 460 provided alongthe direction in which the second gate electrode 433 is extended anddisposed and the length of the second depletion forming layer 415 may beprovided in the same length.

The third passivation film 323 may comprise an insulating material. Forexample, the third passivation film 323 may comprise a single layer ormultiple layers comprising at least one material among a silicon-basedoxide, a silicon nitride, a metal oxide containing Al₂O₃, and an organicinsulator.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 324 disposed on the third passivationfilm 323. The fourth passivation film 324 may be disposed on the firstsource electrode 371, the first drain electrode 372, the second sourceelectrode 471, and the second drain electrode 472.

For example, the fourth passivation film 324 may comprise a single layeror multiple layers containing at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide containing Al₂O₃, and anorganic insulating material.

The thin film transistor substrate according to an embodiment maycomprise a lower electrode 486 disposed on the driving thin filmtransistor 430. The lower electrode 486 may be electrically connected tothe driving thin film transistor 430. The lower electrode 486 may beelectrically connected to the second drain electrode 472 of the drivingthin film transistor 430. The lower electrode 486 may be disposed on thefourth passivation film 324. The lower electrode 486 may be electricallyconnected to the second drain electrode 472 through a contact holeprovided in the fourth passivation film 324. A lower surface of thelower electrode 486 may be disposed in contact with an upper surface ofthe second drain electrode 472.

In addition, the thin film transistor substrate according to anembodiment may comprise a fifth passivation film 325 disposed on thefourth passivation film 324. The light-emitting layer 488 may bedisposed on the lower electrode 486. An upper electrode 487 may bedisposed on the light-emitting layer 488. The light-emitting layer 488and the upper electrode 487 may be disposed on the fifth passivationfilm 325. A first region of the light-emitting layer 488 may be disposedon the fifth passivation film 325, and a second region of thelight-emitting layer 488 may be disposed in contact with an uppersurface of the lower electrode 486 through a contact hole provided inthe fifth passivation film 325. The light-emitting layer 488 may emitlight of any one of red, green, blue, and white as an example. Thelight-emitting layer 488 may be provided with an organic material as anexample.

The lower electrode 486 and the upper electrode 487, for example, maycomprise one material selected from ITO, ITO/Ag, ITO/Ag/ITO, andITO/Ag/IZO, or an alloy containing the material. The lower electrode 486and the upper electrode 487 may comprise different materials. One of theupper electrode 486 and the lower electrode 487 may be formed of atransparent electrode, and light emitted from the light-emitting layer488 in a direction of the transparent electrode may be emitted to theoutside.

The thin film transistor substrate according to an embodiment maycomprise a first black matrix 340 between the substrate 355 and thefirst channel layer 360. A width of the first channel layer 360 may beprovided to be equal to a width of the first black matrix 340. The firstblack matrix 340 may be provided in a single layer or multiple layersincluding at least one material selected from among a Si-based material,a Ga-based material, an Al-based material, and an organic material. Thefirst black matrix 340 may block light incident on the switching thinfilm transistor 330. Accordingly, it is possible to prevent theswitching thin film transistor 330 from deteriorating due to a photocurrent or the like.

The thin film transistor substrate according to an embodiment maycomprise a second black matrix 440 between the substrate 355 and thesecond channel layer 460. A width of the second channel layer 460 may beprovided to be equal to a width of the second black matrix 440. Thesecond black matrix 440 may be provided in a single layer or multiplelayers including at least one material selected from among a Si-basedmaterial, a Ga-based material, an Al-based material, and an organicmaterial. The second black matrix 440 may block light incident on thedriving thin film transistor 430. Accordingly, it is possible to preventthe driving thin film transistor 430 from deteriorating due to a photocurrent or the like.

According to an embodiment, the bonding layer 350 may be disposedbetween the substrate 355 and the first channel layer 360. The bondinglayer 350 may be disposed between the substrate 355 and the first blackmatrix 340. The bonding layer 350 may be disposed between the substrate355 and the second channel layer 460. The bonding layer 350 may bedisposed between the substrate 355 and the second black matrix 440. Forexample, the bonding layer 350 may be disposed on an entire region ofthe substrate 355.

FIG. 45 is a circuit diagram equivalently illustrating one pixel in thethin film transistor substrate described with reference to FIGS. 42 to44.

As shown in FIG. 45, a pixel of the thin film transistor substrateaccording to an embodiment of the present invention may comprise anorganic light-emitting diode (OLED), a data line D and a gate line Gcrossing each other, a switching thin film transistor 330 forsequentially transmitting data of scan pulse SP on the gate line G to apixel, a driving thin film transistor 430 generating a current by avoltage between a gate and a source terminal, and a storage capacitorCst for storing and maintaining data for a predetermined time. In thisway, the structure constituted by two transistors 330 and 430 and onecapacitor Cst may be simply referred to as a 2T-1C structure.

The switching thin film transistor 330 is turned on in response to ascan pulse SP from the gate line G, thereby conducting a current pathbetween its source electrode and drain electrode. During a gate on-timeperiod of the switching thin film transistor 330, a data voltage fromthe data line D passes through the source electrode and the drainelectrode of the switching thin film transistor 330 and is applied tothe gate electrode of the driving thin film transistor 430 and thestorage capacitor Cst. The driving thin film transistor 430 controls acurrent flowing to the OLED according to a voltage difference betweenits gate electrode and source electrode. The storage capacitor Cstconstantly maintains a voltage supplied to the gate electrode of thedriving thin film transistor 430 during one frame period by storing thedata voltage applied to its one side electrode. A driving power supplyline VDD may be connected to the source electrode of the driving thinfilm transistor 430. The OLED provided in the structure as shown in FIG.45 may be connected between the drain electrode of the driving thin filmtransistor 430 and a low potential driving voltage source VSS. Inaddition, the OLED may be disposed to be connected between the sourceelectrode of the driving thin film transistor 430 and the driving powersupply line VDD.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 46 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 46, in the description of the thin filmtransistor substrate according to an embodiment, description of a partoverlapping with those described with reference to FIGS. 1 to 45 may beomitted. An embodiment shown in FIG. 46 differs from that of each ofFIGS. 42 to 45 in the bonding layer structure.

As shown in FIG. 46, a first bonding layer 353 and a second bondinglayer 453 may be provided on the substrate 355. The first bonding layer353 may be disposed between the substrate 355 and the first black matrix340. For example, a width of the first bonding layer 353 may be providedto be equal to a width of the first black matrix 340. For example, thewidth of the first bonding layer 353 may be provided to be equal to awidth of the first channel layer 360. The second bonding layer 453 maybe disposed between the substrate 355 and the second black matrix 440.For example, a width of the second bonding layer 453 may be provided tobe equal to a width of the second black matrix 440. For example, thewidth of the second bonding layer 453 may be provided to be equal to awidth of the second channel layer 460.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355. A lower surface of the second passivationfilm 322 may be disposed in contact with an upper surface of thesubstrate 355. In a region where the first bonding layer 350 is notprovided, the second passivation film 322 may be disposed in directcontact with the substrate 355. In a region where the second bondinglayer 450 is not provided, the second passivation film 322 may bedisposed in direct contact with the substrate 355.

As described above, according to the embodiment shown in FIG. 46, ascompared with the embodiment shown in FIG. 43, since the secondpassivation film 322 and the substrate 355 may be disposed in directcontact with each other, a layer provided between the second passivationfilm 322 and the substrate 355 (for example, an illustrated bondinglayer in FIG. 43) may be eliminated. Accordingly, according to theembodiment, since an interface between different material layers isreduced on a light path where light travels, light loss due toreflection/refraction at the interface may be reduced.

The first bonding layer 353 and the second bonding layer 453 accordingto an embodiment may comprise at least one of a reflective layer, ametal bonding layer, an organic bonding layer, and an insulating layeras an example. The reflective layer may be disposed on the substrate355, the metal bonding layer may be disposed on the reflective layer,and the insulating layer may be disposed on the metal bonding layer. Forexample, the first bonding layer 353 and the second bonding layer 453may comprise at least one of the metal bonding layer and the organicbonding layer, and the reflective layer and the insulating layer may becomprised selectively.

The insulating layer may complement the leakage characteristics of thefirst channel layer 360 and the second channel layer 460. For example,the insulating layer may comprise a single layer or multiple layersincluding at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide including Al₂O₃, and an organicinsulating material as an example.

The metal bonding layer or the organic bonding layer may be provided forbonding with the substrate 355 disposed thereunder. For example, themetal bonding layer may comprise at least one material selected from thegroup consisting of gold (Au), tin (Sn), indium (In), nickel (Ni),silver (Ag), and copper (Cu), or an alloy thereof. For example, theorganic bonding layer may comprise at least one material selected fromthe group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, andthe like.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

Meanwhile, according to an embodiment, for example, when the firstbonding layer 353 and the second bonding layer 453 comprise the metalbonding layer and the reflective layer, the first black matrix 340 andthe second black matrix 440 may be omitted.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 47 is view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 47, in the description of the thin filmtransistor substrate according to the embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to46 may be omitted. An embodiment shown in FIG. 47 differs from that ofeach of FIG. 45 in that a transfer process is not applied and a thinfilm transistor is provided on a growth substrate.

As shown in FIG. 47, the thin film transistor substrate according to theembodiment may comprise a growth substrate 310 as a substrate instead ofa support substrate used in the transfer process. For example, thegrowth substrate 310 may comprise at least one of group consisting ofsapphire, SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

A first black matrix 345 and a second black matrix 445 may be disposedon the growth substrate 310. The first black matrix 345 is disposed onthe growth substrate 310 and may prevent light from being incident onthe first channel layer 360. The first black matrix 345 may be providedwith a material that absorbs or reflects visible rays as an example.Thus, according to the embodiment, light is incident on the firstchannel layer 360 and it is possible to prevent a switching thin filmtransistor 330 from being deteriorated due to a photo current or thelike. The second black matrix 445 is disposed on the growth substrate310 and may prevent light from being incident on the second channellayer 460. The second black matrix 445 may be provided with a materialthat absorbs or reflects visible rays as an example. Thus, according tothe embodiment, light is incident on the second channel layer 460 and itis possible to prevent a driving thin film transistor 330 from beingdeteriorated due to a photo current or the like.

For example, the first black matrix 345 and the second black matrix 445may be provided in a single layer or multiple layers including at leastone material selected from among a Si-based material, a Ga-basedmaterial, an Al-based material, and an organic material. The first blackmatrix 345 and the second black matrix 445 may selectively comprise amaterial such as Si, GaAs, or the like.

According to an embodiment, a first buffer layer 347 may be provided onthe first black matrix 345. The first buffer layer 347 may be providedbetween the first black matrix 345 and the first channel layer 360. Thefirst buffer layer 347 may help a growth of a nitride semiconductorlayer constituting the first channel layer 360. A second buffer layer447 may be provided on the second black matrix 445. The second bufferlayer 447 may be provided between the second black matrix 445 and thesecond channel layer 460. The second buffer layer 447 may help a growthof a nitride semiconductor layer constituting the second channel layer460. For example, the first buffer layer 347 and the second buffer layer447 may comprise a single layer or multiple layers including at leastone material selected from the group consisting of AlN, AlInN, andAlGaN.

For example, a width of the first black matrix 345 may be provided to beequal to a width of the first buffer layer 347. For example, the widthof the first black matrix 345 may be provided to be equal to a width ofthe first channel layer 360. The width of the first buffer layer 347 maybe provided to be equal to the width of the first channel layer 360. Awidth of the second black matrix 445 may be provided to be equal to awidth of the second buffer layer 447. For example, the width of thesecond black matrix 445 may be provided to be equal to a width of thesecond channel layer 460. The width of the second buffer layer 447 maybe provided to be equal to the width of the second channel layer 460.

According to an embodiment, the second passivation film 322 may bedisposed on the growth substrate 310. A lower surface of the secondpassivation film 322 may be disposed in contact with an upper surface ofthe growth substrate 310. In a region where the first black matrix 345and the second black matrix 445 is not provided, the second passivationfilm 322 may be disposed in direct contact with the growth substrate310.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 48 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. FIG. 48 is a cross-sectional view taken along line D-D of thethin film transistor substrate shown in FIG. 42. The thin filmtransistor substrate shown in FIG. 48 is an embodiment to which aswitching thin film transistor having a double gate structure isapplied, and description of contents overlapping with those describedwith reference to FIGS. 1 to 47 may be omitted.

The thin film transistor substrate according to an embodiment maycomprise a switching thin film transistor 530 and a driving thin filmtransistor 630. The switching thin film transistor 530 may receive asignal from a gate line 341 and a data line 373 and may provide a gatesignal and a data signal to a corresponding pixel. A gate electrode 635of the driving thin film transistor 630 may be electrically connected tothe drain electrode 372 of the switching thin film transistor 530.

As shown in FIG. 48, the thin film transistor substrate according to anembodiment of the present invention may comprise a substrate 355, theswitching thin film transistor 530 disposed on the substrate 355, thedriving thin film transistor 630, and a light-emitting layer 488electrically connected to the driving thin film transistor 630.

The switching thin film transistor 530 according to an embodiment maycomprise a first depletion forming layer 315, a first gate electrode535, a first double gate electrode 536, a first channel layer 360, afirst source electrode 371, and a first drain electrode 372. The firstsource electrode 371 may be electrically connected to a first region ofthe first channel layer 360. The first source electrode 371 may beelectrically connected to an upper surface of the first channel layer360. The first drain electrode 372 may be electrically connected to asecond region of the first channel layer 360. The first drain electrode372 may be electrically connected to the upper surface of the firstchannel layer 360. The first gate electrode 535 may be disposed on thefirst channel layer 360. The first double gate electrode 536 may bedisposed under the first channel layer 360. The first depletion forminglayer 315 may be disposed on between the first region and the secondregion of the first channel layer 360. The first depletion forming layer315 may be disposed between the first channel layer 360 and the firstgate electrode 535.

The driving thin film transistor 630 according to an embodiment maycomprise a second depletion forming layer 415, a second gate electrode635, a second double gate electrode 636, a second channel layer 460, asecond source electrode 471, and a second drain electrode 472. Thesecond source electrode 471 may be electrically connected to a firstregion of the second channel layer 460. The second source electrode 471may be electrically connected to an upper surface of the second channellayer 460. The second drain electrode 472 may be electrically connectedto a second region of the second channel layer 460. The second drainelectrode 472 may be electrically connected to the upper surface of thesecond channel layer 460. The second gate electrode 635 may be disposedon the second channel layer 460. The second depletion forming layer 415may be disposed on between the first region and the second region of thesecond channel layer 460. The second depletion forming layer 415 may bedisposed between the second channel layer 460 and the second gateelectrode 635.

The first channel layer 360 and the second channel layer 460 may beprovided with, for example, a Group III-V compound semiconductor. Forexample, the first channel layer 360 and the second channel layer 460may be provided with a semiconductor material having an empiricalformula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The firstchannel layer 360 and the second channel layer 460 may comprise a singlelayer or multiple layers selected from, for example, GaN, AlN, AlGaN,InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and so on.The first channel layer 360 and the second channel layer 460 may beformed of different materials.

The first channel layer 360 and the second channel layer 460 may eachcomprise first nitride semiconductor layers 361 and 461 and secondnitride semiconductor layers 362 and 462. The first nitridesemiconductor layers 361 and 461 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layers 362 and 462 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).

According to the first channel layer 360 and the second channel layer460 according to an embodiment, the first nitride semiconductor layers361 and 461 may comprise a GaN semiconductor layer, and the secondnitride semiconductor layers 362 and 462 may comprise an AlGaNsemiconductor layer. The second nitride semiconductor layer 362 of thefirst channel layer 360 may be disposed between the first nitridesemiconductor layer 361 and the first depletion forming layer 315. Thesecond nitride semiconductor layer 462 of the second channel layer 460may be disposed between the first nitride semiconductor layer 461 andthe second depletion forming layer 415.

The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided with, for example, a group III-V compoundsemiconductor. For example, the first depletion forming layer 315 andthe second depletion forming layer 415 may be provided with asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The first depletionforming layer 315 and the second depletion forming layer 415 maycomprise a single layer or multiple layers selected from, for example,GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP,AlGaInP and so on. The first depletion forming layer 315 and the seconddepletion forming layer 415 may comprise a nitride semiconductor layerdoped with a p-type dopant. For example, the first depletion forminglayer 315 and the second depletion forming layer 415 may comprise a GaNsemiconductor layer doped with a p-type dopant or an AlGaN semiconductorlayer doped with a p-type dopant. The first depletion forming layer 315and the second depletion forming layer 415 may comprise a single layeror multiple layers provided with, for example, a semiconductor materialhaving an empirical formula of p-Al_(x)Ga_(1-x)N (0≥x≥0.3).

The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided in a thickness of 2 to 300 nm as an example.The first depletion forming layer 315 and the second depletion forminglayer 415 may be provided in a thickness of at least 2 nm in order toprovide a depletion region at two-dimensional electron gas (2 DEG)provided at the first channel layer 360 and the second channel layer460. In addition, the first depletion forming layer 315 and the seconddepletion forming layer 415 may be provided in a thickness of 30 nm ormore in consideration of a thickness deviation according to amanufacturing process. In addition, the first depletion forming layer315 and the second depletion forming layer 415 may be provided in athickness of 200 nm or less in consideration of a thickness deviationaccording to a manufacturing process. The first depletion forming layer315 and the second depletion forming layer 415 may be provided in athickness of 50 to 100 nm as an example.

The first depletion forming layer 315 and the second depletion forminglayer 415 may comprise different materials. Substances added to thefirst depletion forming layer 315 and the second depletion forming layer415, and addition amounts of the added substances may be different fromeach other.

The first depletion forming layer 315 and the second depletion forminglayer 415 may serve to form a depletion region in a two-dimensionalelectron gas (2 DEG) provided in the first channel layer 360 and thesecond channel layer 460. The energy bandgap of a portion of the secondnitride semiconductor layer 362 positioned thereunder may be increasedby the first depletion forming layer 315. As a result, the depletionregion of the 2 DEG may be provided at a portion of the first channellayer 360 corresponding to the first depletion forming layer 315.Therefore, a region corresponding to the position in which the firstdepletion forming layer 315 is disposed in the 2 DEG provided at thefirst channel layer 360 may be cut off. A region in which the 2 DEG iscut off at the first channel layer 360 may be referred to as a cut-offregion, and, for example, a cut-off region may be formed at the secondnitride semiconductor layer 362. The switching thin film transistor 530may have a normally-off characteristic due to such a cut-off region.When a voltage equal to or higher than a threshold voltage is applied tothe first gate electrode 333, the 2 DEG is generated at the cut-offregion and the switching thin film transistor 530 is turned on. When achannel formed at a lower portion of the first gate electrode 333 isturned on, a current may flow via the 2 DEG formed at the first channellayer 360. Accordingly, the current flow from the first region to thesecond region of the first channel layer 360 may be controlled accordingto a voltage applied to the first gate electrode 535 and the firstdouble gate electrode 536.

The energy bandgap of a portion of the second nitride semiconductorlayer 462 positioned thereunder may be increased by the second depletionforming layer 415. As a result, the depletion region of the 2 DEG may beprovided at a portion of the second channel layer 460 corresponding tothe second depletion forming layer 415. Therefore, a regioncorresponding to the position in which the second depletion forminglayer 415 is disposed in the 2 DEG provided at the second channel layer460 may be cut off. A region in which the 2 DEG is cut off at the secondchannel layer 460 may be referred to as a cut-off region, and, forexample, a cut-off region may be formed at the second nitridesemiconductor layer 462. The driving thin film transistor 630 may have anormally-off characteristic due to such a cut-off region. When a voltageequal to or higher than a threshold voltage is applied to the secondgate electrode 635, the 2 DEG is generated at the cut-off region and thedriving thin film transistor 630 is turned on. When a channel formed ata lower portion of the second gate electrode 635 is turned on, a currentmay flow via the 2 DEG formed at the second channel layer 460.Accordingly, the current flow from the first region to the second regionof the second channel layer 460 may be controlled according to a voltageapplied to the second gate electrode 635 and the second double gateelectrode 636.

According to an embodiment, the first double gate electrode 536 may bedisposed under the first channel layer 360. The first gate electrode 535and the first double gate electrode 536 may be disposed to be overlappedwith each other in a vertical direction. According to an embodiment, thefirst gate electrode 535 and the first double gate electrode 536 aredisposed below and above the first channel layer 360, so that a currentflow in the first channel layer 360 may be controlled to be efficientand reliable. The second double gate electrode 636 may be disposed underthe second channel layer 460. The second gate electrode 635 and thesecond double gate electrode 636 may be disposed to be overlapped witheach other in a vertical direction. According to an embodiment, thesecond gate electrode 635 and the second double gate electrode 636 aredisposed below and above the second channel layer 460, so that a currentflow in the second channel layer 460 may be controlled to be efficientand reliable.

Meanwhile, in the description of the embodiment with reference to FIG.48, it is described based on the case that all of the switching thinfilm transistor and the driving thin film transistor may be provided asa double gate structure, however, at least one of the switching thinfilm transistor and the driving thin film transistor may be provided asa double gate structure.

The substrate 355 may comprise a transparent substrate. The substrate355 may be provided with a transparent substrate having a thickness of0.1 mm to 3 mm as an example. In addition, the thickness of thesubstrate 355 may be changed according to application and size of anapplied display device and may be selected within a thickness range of0.4 to 1.1 mm. For example, the substrate 355 may be provided in athickness of 0.6 to 0.8 mm. The substrate 355 may comprise at least onematerial selected from materials including silicon, glass, polyimide,and plastic.

The substrate 355 may comprise a flexible substrate. The substrate 355is a substrate to be used in a transfer process, and serves to supportthe switching thin film transistor 530 and the driving thin filmtransistor 630. In addition, the thin film transistor substrateaccording to an embodiment may comprise a bonding layer 350 providedbetween the substrate 355 and the switching thin film transistor 530.The bonding layer 350 may be disposed between the substrate 355 and thedriving thin film transistor 630.

The bonding layer 350 may comprise an organic material. The bondinglayer 350 may be provided with a transparent material. The bonding layer350 may be provided with, for example, a material having a transmittanceof 70% or more. The bonding layer 350 may comprise an organic insulatingmaterial. The bonding layer 350 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 350 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer350 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer350 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The switching thin film transistor 530 according to an embodiment maycomprise a first source contact portion 331 disposed on the first regionof the first channel layer 360 and a first drain contact portion 332disposed on the second region of the first channel layer 360. The firstsource contact portion 331 may be disposed in contact with the firstregion of the first channel layer 360. The first drain contact portion332 may be disposed in contact with the second region of the firstchannel layer 360.

A switching thin film transistor 530 according to an embodiment maycomprise a first gate wiring 341 disposed on the first gate electrode535. The first gate wiring 341 may be electrically connected to thefirst gate electrode 535. A lower surface of the first gate wiring 341may be disposed in contact with an upper surface of the first gateelectrode 535.

The first source electrode 371 may be electrically connected to thefirst source contact portion 331. The first source electrode 371 may bedisposed in contact with an upper surface of the first source contactportion 331. For example, the first source electrode 371 may beelectrically connected to a first region of the first channel layer 360via the first source contact portion 331. The first drain electrode 372may be electrically connected to the first drain contact portion 332.The first drain electrode 372 may be disposed in contact with an uppersurface of the first drain contact portion 332. For example, the firstdrain electrode 372 may be electrically connected to a second region ofthe first channel layer 360 via the first drain contact portion 332.

The driving thin film transistor 630 according to an embodiment maycomprise a second source contact portion 431 disposed on the firstregion of the second channel layer 460 and a second drain contactportion 432 disposed on the second region of the second channel layer460. The second source contact portion 431 may be disposed in contactwith the first region of the second channel layer 460. The second draincontact portion 432 may be disposed in contact with the second region ofthe second channel layer 460.

A driving thin film transistor 630 according to an embodiment maycomprise a second gate wiring 441 disposed on the second gate electrode635. The second gate wiring 441 may be electrically connected to thesecond gate electrode 635. A lower surface of the second gate wiring 441may be disposed in contact with an upper surface of the second gateelectrode 635.

The second source electrode 471 may be electrically connected to thesecond source contact portion 431. The second source electrode 471 maybe disposed in contact with an upper surface of the second sourcecontact portion 431. For example, the second source electrode 471 may beelectrically connected to a first region of the second channel layer 460via the second source contact portion 431. The second drain electrode472 may be electrically connected to the second drain contact portion432. The second drain electrode 472 may be disposed in contact with anupper surface of the second drain contact portion 432. For example, thesecond drain electrode 472 may be electrically connected to a secondregion of the second channel layer 460 via the second drain contactportion 432.

The first source contact portion 331 and the first drain contact portion332 may be provided with a material in ohmic contact with the firstchannel layer 360. The first source contact portion 331 and the firstdrain contact portion 332 may comprise a material in ohmic contact withthe second nitride semiconductor layer 362. The second source contactportion 431 and the second drain contact portion 432 may be providedwith a material in ohmic contact with the second channel layer 460. Thesecond source contact portion 431 and the second drain contact portion432 may comprise a material in ohmic contact with the second nitridesemiconductor layer 462. For example, the first source contact portion331, the first drain contact portion 332, the second source contactportion 431, and the second drain contact portion 432 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first source contact portion331, the first drain contact portion 332, the second source contactportion 431 and the second drain contact portion 432 may be provided ina thickness of 0.1 to 1 μm as an example. The first source contactportion 331, the first drain contact portion 332, the second sourcecontact portion 431, and the second drain contact portion 432 do notneed to serve to spread a current as a layer for contacting with thefirst channel layer 360 and the second channel layer 460. Accordingly,the first source contact portion 331, the first drain contact portion332, the second source contact portion 431, and the second drain contactportion 432 may be provided in a thickness of 1 μm or less.

The first gate electrode 535 may be provided with a material in ohmiccontact with the first depletion forming layer 315. The second gateelectrode 635 may be provided with a material in ohmic contact with thesecond depletion forming layer 415. For example, the first gateelectrode 535 and the second gate electrode 635 may be provided with amaterial in ohmic contact with a p-type nitride layer. The first gateelectrode 535 and the second gate electrode 635 may comprise a singlelayer or multiple layers comprising at least one material selected fromthe group consisting of tungsten (W), tungsten silicon (WSi2), titaniumnitride (TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd),nickel (Ni), and platinum (Pt). The first gate electrode 535 and thesecond gate electrode 635 may be provided in a thickness of 0.1 to 1 μmas an example. The first gate electrode 535 and the second gateelectrode 635 do not need to serve to spread a current as a layer forcontacting with the first depletion forming layer 315 and the seconddepletion forming layer 415. Accordingly, the first gate electrode 535and the second gate electrode 635 may be provided in a thickness of 1 μmor less.

The first gate wiring 341 and the second gate wiring 441 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first gate wiring 341 and thesecond gate wiring 441 may be provided in a thickness of 0.1 to 3 μm asan example. The first gate wiring 341 and the second gate wiring 441serve to sequentially apply a voltage to a plurality of transistors.Accordingly, the first gate wiring 341 and the second gate wiring 441may be provided to be thicker than a thickness of the first gateelectrode 535 and the second gate electrode 635.

The first source electrode 371, the first drain electrode 372, thesecond source electrode 471, and the second drain electrode 472 maycomprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of aluminum (Al), analuminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy (Cualloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold(Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), a titaniumalloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi),and copper/molybdenum titanium (Cu/MoTi). The first source electrode371, the first drain electrode 372, the second source electrode 471, andthe second drain electrode 472 may be provided in a thickness of 0.1 to3 μm as an example. The first source electrode 371 and the second sourceelectrode 471 serve to sequentially apply a voltage to the plurality oftransistors. Accordingly, the first source electrode 371 and the secondsource electrode 471 may be provided to be thicker than a thickness ofthe first source contact portion 331 and the second source contactportion 431. Also, the first drain electrode 372 and the second drainelectrode 472 may be provided to be thicker than a thickness of thefirst drain contact portion 332 and the second drain contact portion432.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 321 and 421 disposed on the firstchannel layer 360 and the second channel layer 460. The firstpassivation film 321 and 421 may be disposed on the second nitridesemiconductor layer 362 of the first channel layer 360 and the secondnitride semiconductor layer 462 of the second channel layer 460. A lowersurface of the first passivation film 321 and 421 may be disposed incontact with an upper surface of the second nitride semiconductor layer362 of the first channel layer 360 and the second nitride semiconductorlayer 462 of the second channel layer 460. The first passivation film321 and 421 may be disposed on the first depletion forming layer 315 andthe second depletion forming layer 415. The first passivation film 321and 421 may be disposed at a side surface of the first depletion forminglayer 315 and the second depletion forming layer 415. The firstpassivation film 321 and 421 may be disposed so as to surround the sidesurface of the first depletion forming layer 315 and the seconddepletion forming layer 415.

According to an embodiment, the first source contact portion 331 may bedisposed to pass through the first passivation film 321. The firstsource contact portion 331 may be disposed to be surrounded by the firstpassivation film 321. The first source contact portion 331 may bedisposed to pass through the first passivation film 321 and provided incontact with the first region of the first channel layer 360. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321. The first drain contact portion 332 may bedisposed to be surrounded by the first passivation film 321. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321 and provided in contact with the second region ofthe first channel layer 360.

According to an embodiment, the second source contact portion 431 may bedisposed to pass through the first passivation film 421. The secondsource contact portion 431 may be disposed to be surrounded by the firstpassivation film 421. The second source contact portion 431 may bedisposed to pass through the first passivation film 421 and provided incontact with the first region of the second channel layer 460. Thesecond drain contact portion 432 may be disposed to pass through thefirst passivation film 421. The second drain contact portion 432 may bedisposed to be surrounded by the first passivation film 421. The seconddrain contact portion 432 may be disposed to pass through the firstpassivation film 421 and provided in contact with the second region ofthe second channel layer 460.

The first passivation film 321 and 421 may be provided with aninsulating material. The first passivation film 321 and 421 may comprisea single layer or multiple layers comprising at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide comprisingAl₂O₃, and an organic insulating material as an example.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355 and the first passivation film 321 and421. The first gate electrode 535 may be disposed to pass through atleast one of the first passivation film 321 and the second passivationfilm 322. For example, the first gate electrode 535 may be disposed topass through the first passivation film 321 and the second passivationfilm 322. The first gate electrode 535 may pass through at least one ofthe first passivation film 321 and the second passivation film 322 andbe disposed in contact with the first depletion forming layer 315. Forexample, the first gate electrode 535 may pass through the firstpassivation film 321 and the second passivation film 322 and be disposedin contact with the first depletion forming layer 315. The first gatewiring 341 may be disposed on the second passivation film 322 and beelectrically connected to the first gate electrode 535. The second gateelectrode 635 may be disposed to pass through at least one of the firstpassivation film 321 and the second passivation film 322. For example,the second gate electrode 635 may be disposed to pass through the firstpassivation film 321 and the second passivation film 322. The secondgate electrode 635 may pass through at least one of the firstpassivation film 321 and the second passivation film 322 and be disposedin contact with the second depletion forming layer 415. For example, thesecond gate electrode 635 may pass through the first passivation film321 and the second passivation film 322 and be disposed in contact withthe second depletion forming layer 415. The second gate wiring 441 maybe disposed on the second passivation film 322 and be electricallyconnected to the second gate electrode 635.

The second passivation film 322 may be provided with an insulatingmaterial. The second passivation film 322 may comprise a single layer ormultiple layers including at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide including Al₂O₃, and anorganic insulating material as an example.

According to an embodiment, a third passivation film 323 may be disposedon the second passivation film 322. The third passivation film 323 maybe disposed on the second passivation film 322, the first gate wiring341, and the second gate wiring 342. The first gate wiring 341 may bedisposed in contact with the first gate electrode 535 thereon andprovided to be surrounded by the third passivation film 323. The secondgate wiring 441 may be disposed in contact with the second gateelectrode 635 thereon and provided to be surrounded by the thirdpassivation film 323.

The first source electrode 371 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the first source contact portion 331. The first sourceelectrode 371 may comprise a first region disposed on the thirdpassivation film 323. The first source electrode 371 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The first drain electrode 372 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the first drain contact portion332. The first drain electrode 372 may comprise a first region disposedon the third passivation film 323. The first drain electrode 372 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

The second source electrode 471 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the second source contact portion 431. The second sourceelectrode 471 may comprise a first region disposed on the thirdpassivation film 323. The second source electrode 471 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The second drain electrode 472 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the second drain contact portion432. The second drain electrode 472 may comprise a first region disposedon the third passivation film 323. The second drain electrode 472 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

The first double gate electrode 536 may be disposed under the firstchannel layer 360. The first double gate electrode 536 may be disposedunder the first nitride semiconductor layer 361. A sixth passivationfilm 526 may be disposed under the first double gate electrode 536 andthe first channel layer 360. The first double gate electrode 536 may bedisposed in contact with a lower surface of the first channel layer 360.The first double gate electrode 536 may be in Schottky contact with thefirst nitride semiconductor layer 361. The first double gate electrode536 may comprise a single layer or multiple layers including at leastone material selected from the group consisting of nickel (Ni), platinum(Pt), gold (Au), and palladium (Pd), or an alloy thereof. For example,the Schottky contact may be implemented by plasma treatment of the firstchannel layer 360.

The second double gate electrode 636 may be disposed under the secondchannel layer 460. The second double gate electrode 636 may be disposedunder the first nitride semiconductor layer 461. A sixth passivationfilm 626 may be disposed under the second double gate electrode 636 andthe second channel layer 460. The second double gate electrode 636 maybe disposed in contact with a lower surface of the second channel layer460. The second double gate electrode 636 may be in Schottky contactwith the first nitride semiconductor layer 461. The second double gateelectrode 636 may comprise a single layer or multiple layers includingat least one material selected from the group consisting of nickel (Ni),platinum (Pt), gold (Au), and palladium (Pd), or an alloy thereof. Forexample, the Schottky contact may be implemented by plasma treatment ofthe second channel layer 460.

The first gate electrode 535 and the first double gate electrode 536 maybe electrically connected. The second gate electrode 635 and the seconddouble gate electrode 636 may be electrically connected. The seconddrain electrode 372 of the switching thin film transistor 530 and thesecond gate electrode 635 of the driving thin film transistor 630 may beelectrically connected.

The third passivation film 323 may comprise an insulating material. Thethird passivation film 323 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 324 disposed on the third passivationfilm 323. The fourth passivation film 324 may be disposed on the firstsource electrode 371, the first drain electrode 372, the second sourceelectrode 471, and the second drain electrode 472.

The fourth passivation film 324 may comprise a single layer or multiplelayers comprising at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide comprising Al₂O₃, and an organicinsulating material as an example.

The thin film transistor substrate according to an embodiment maycomprise a lower electrode 486 disposed on the driving thin filmtransistor 630. The lower electrode 486 may be electrically connected tothe driving thin film transistor 630. The lower electrode 486 may beelectrically connected to the second drain electrode 472 of the drivingthin film transistor 630. The lower electrode 486 may be disposed on thefourth passivation film 324. The lower electrode 486 may be electricallyconnected to the second drain electrode 472 through a contact holeprovided in the fourth passivation film 324. A lower surface of thelower electrode 486 may be disposed in contact with an upper surface ofthe second drain electrode 472.

In addition, the thin film transistor substrate according to anembodiment may comprise a fifth passivation film 325 disposed on thefourth passivation film 324. The light-emitting layer 488 may bedisposed on the lower electrode 486. An upper electrode 487 may bedisposed on the light-emitting layer 488. The light-emitting layer 488and the upper electrode 487 may be disposed on the fifth passivationfilm 325. A first region of the light-emitting layer 488 may be disposedon the fifth passivation film 325, and a second region of thelight-emitting layer 488 may be disposed in contact with an uppersurface of the lower electrode 486 through a contact hole provided inthe fifth passivation film 325. The light-emitting layer 488 may emitlight of any one of red, green, blue, and white as an example. Thelight-emitting layer 488 may be provided with an organic material as anexample.

The lower electrode 486 and the upper electrode 487, for example, maycomprise one material selected from ITO, ITO/Ag, ITO/Ag/ITO, andITO/Ag/IZO, or an alloy containing the material. The lower electrode 486and the upper electrode 487 may comprise different materials. One of theupper electrode 486 and the lower electrode 487 may be formed of atransparent electrode, and light emitted from the light-emitting layer488 in a direction of the transparent electrode may be emitted to theoutside.

The thin film transistor substrate according to an embodiment maycomprise a first black matrix 546 between the substrate 355 and thefirst channel layer 360. The first black matrix 546 may be disposedbetween the substrate 355 and the sixth passivation film 526. The firstblack matrix 546 may be disposed between the substrate 355 and the firstdouble gate electrode 536. The first black matrix 546 may be disposed ina shape corresponding to a shape of a lower portion of the sixthpassivation film 526. A width of the first channel layer 360 may beprovided to be equal to a width of the first black matrix 546. The firstblack matrix 546 may be provided in a single layer or multiple layersincluding at least one material selected from among a Si-based material,a Ga-based material, an Al-based material, and an organic material. Thefirst black matrix 546 may block light incident on the switching thinfilm transistor 530. Accordingly, it is possible to prevent theswitching thin film transistor 530 from deteriorating due to a photocurrent or the like.

The thin film transistor substrate according to an embodiment maycomprise a second black matrix 646 between the substrate 355 and thesecond channel layer 460. The second black matrix 646 may be disposedbetween the substrate 355 and the sixth passivation film 626. The secondblack matrix 646 may be disposed between the substrate 355 and thesecond double gate electrode 636. The second black matrix 646 may bedisposed in a shape corresponding to a shape of a lower portion of thesixth passivation film 626. A width of the second channel layer 460 maybe provided to be equal to a width of the second black matrix 646. Thesecond black matrix 646 may be provided in a single layer or multiplelayers including at least one material selected from among a Si-basedmaterial, a Ga-based material, an Al-based material, and an organicmaterial. The second black matrix 646 may block light incident on thedriving thin film transistor 630. Accordingly, it is possible to preventthe driving thin film transistor 630 from deteriorating due to a photocurrent or the like.

According to an embodiment, the bonding layer 350 may be disposedbetween the substrate 355 and the firsts channel layer 360. The bondinglayer 350 may be disposed between the substrate 355 and the first blackmatrix 546. The bonding layer 350 may be disposed between the substrate355 and the second channel layer 460. The bonding layer 350 may bedisposed between the substrate 355 and the second black matrix 646. Forexample, the bonding layer 350 may be disposed on an entire region ofthe substrate 355. The bonding layer 350 may be disposed in contact withthe second passivation film 322. An upper surface of the bonding layer350 and a lower surface of the second passivation film 322 may bedisposed in contact with each other. For example, in a region where thefirst black matrix 346 and the second black matrix are not provided, theupper surface of the first bonding layer 350 and the lower surface ofthe second passivation film 322 may be disposed in direct contact witheach other.

In addition, according to an embodiment, a recess corresponding to aheight and a width of the first double gate electrode 536 and the seconddouble gate electrode 636 may be provided on the bonding layer 350. Apart of the sixth passivation film 526 and 626 may be disposed in atleast a part of an upper portion and a side surface so as to correspondto a cross sectional shape of the first double gate electrode 536 andthe second double gate electrode 636, and provided in the recessedregion. The first black matrix 546 may be disposed in a shapecorresponding to a shape of a lower portion of the sixth passivationfilm 526, and at least a part of the first black matrix 546 may bedisposed in the recessed region. The second black matrix 646 may bedisposed in a shape corresponding to a shape of a lower portion of thesixth passivation film 626, and at least a part of the second blackmatrix 646 may be disposed in the recessed region. At least a part ofthe first double gate electrode 536 and the second double gate electrode636 may be disposed in the recessed region. It is possible to minimizean increase in a thickness of the thin film transistor substrateaccording to providing the first double gate electrode 536 and thesecond double gate electrode 636 with such a structure.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 49 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 49, in the description of the thin filmtransistor substrate according to an embodiment, description of a partoverlapping with those described with reference to FIGS. 1 to 48 may beomitted. An embodiment shown in FIG. 49 differs from that of each ofFIG. 48 in the bonding layer structure.

As shown in FIG. 49, a first bonding layer 553 and a second bondinglayer 653 may be provided on the substrate 355. The first bonding layer553 may be disposed between the substrate 355 and the first black matrix546. For example, a width of the first bonding layer 553 may be providedto be equal to a width of the first black matrix 546. For example, thewidth of the first bonding layer 553 may be provided to be equal to awidth of the first channel layer 360. The second bonding layer 653 maybe disposed between the substrate 355 and the second black matrix 646.For example, a width of the second bonding layer 653 may be provided tobe equal to a width of the second black matrix 646. For example, thewidth of the second bonding layer 653 may be provided to be equal to awidth of the second channel layer 460.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355. A lower surface of the second passivationfilm 322 may be disposed in contact with an upper surface of thesubstrate 355. In a region where the first bonding layer 553 is notprovided, the second passivation film 322 may be disposed in directcontact with the substrate 355. In a region where the second bondinglayer 653 is not provided, the second passivation film 322 may bedisposed in direct contact with the substrate 355.

In addition, according to an embodiment, a recess corresponding to aheight and a width of the first double gate electrode 536 and the seconddouble gate electrode 636 may be provided on the first bonding layer 526and the second bonding layer 626. A part of the sixth passivation film526 and 626 may be disposed in at least a part of an upper portion and aside surface so as to correspond to a cross sectional shape of the firstdouble gate electrode 536 and the second double gate electrode 636, andprovided in the recessed region. The first black matrix 546 may bedisposed in a shape corresponding to a shape of a lower portion of thesixth passivation film 526, and at least a part of the first blackmatrix 546 may be disposed in the recessed region. The second blackmatrix 646 may be disposed in a shape corresponding to a shape of alower portion of the sixth passivation film 626, and at least a part ofthe second black matrix 646 may be disposed in the recessed region. Atleast a part of the first double gate electrode 536 and the seconddouble gate electrode 636 may be disposed in the recessed region. It ispossible to minimize an increase in a thickness of the thin filmtransistor substrate according to providing the first double gateelectrode 536 and the second double gate electrode 636 with such astructure.

As described above, according to the embodiment shown in FIG. 49, ascompared with the embodiment shown in FIG. 48, since the secondpassivation film 322 and the substrate 355 may be disposed in directcontact with each other, a layer provided between the second passivationfilm 322 and the substrate 355 (for example, an illustrated bondinglayer in FIG. 48) may be eliminated. Accordingly, according to theembodiment, since an interface between different material layers isreduced on a light path where light travels, light loss due toreflection/refraction at the interface may be reduced.

The first bonding layer 553 and the second bonding layer 653 accordingto an embodiment may comprise at least one of a reflective layer, ametal bonding layer, an organic bonding layer, and an insulating layeras an example. The reflective layer may be disposed on the substrate355, the metal bonding layer may be disposed on the reflective layer,and the insulating layer may be disposed on the metal bonding layer. Forexample, the first bonding layer 553 and the second bonding layer 653may comprise at least one of the metal bonding layer and the organicbonding layer, and the reflective layer and the insulating layer may becomprised selectively.

The insulating layer may complement the leakage characteristics of thefirst channel layer 360 and the second channel layer 460. For example,the insulating layer may comprise a single layer or multiple layersincluding at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide including Al₂O₃, and an organicinsulating material as an example.

The metal bonding layer or the organic bonding layer may be provided forbonding with the substrate 355 disposed thereunder. For example, themetal bonding layer may comprise at least one material selected from thegroup consisting of gold (Au), tin (Sn), indium (In), nickel (Ni),silver (Ag), and copper (Cu), or an alloy thereof. For example, theorganic bonding layer may comprise at least one material selected fromthe group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, andthe like.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

Meanwhile, according to an embodiment, for example, when the firstbonding layer 553 and the second bonding layer 653 comprise the metalbonding layer and the reflective layer, the first black matrix 546 andthe second black matrix 646 may be omitted.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 50 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. FIG. 50 is a cross-sectional view taken along line D-D of thethin film transistor substrate shown in FIG. 42.

The thin film transistor substrate shown in FIG. 50 is an embodiment towhich a thin film transistor having a gate electrode disposed in arecessed region of a channel layer is applied, and description ofcontents overlapping with those described with reference to FIGS. 1 to49 may be omitted.

The thin film transistor substrate according to an embodiment maycomprise a switching thin film transistor 730 and a driving thin filmtransistor 830. The switching thin film transistor 730 may receive asignal from a first gate line 341 and a first data line 373 and mayprovide a gate signal and a data signal to a corresponding pixel. Asecond gate electrode 833 of the driving thin film transistor 830 may beelectrically connected to the first drain electrode 372 of the switchingthin film transistor 830.

As shown in FIG. 50, the thin film transistor substrate according to anembodiment of the present invention may comprise a substrate 355, theswitching thin film transistor 730 disposed on the substrate 355, thedriving thin film transistor 830, and a light-emitting layer 488electrically connected to the driving thin film transistor 830.

The switching thin film transistor 730 according to an embodiment maycomprise a first gate electrode 733, a first channel layer 760, a firstsource electrode 371, and a first drain electrode 372. The first sourceelectrode 371 may be electrically connected to a first region of thefirst channel layer 760. The first source electrode 371 may beelectrically connected to an upper surface of the first channel layer760. The first drain electrode 372 may be electrically connected to asecond region of the first channel layer 760. The first drain electrode372 may be electrically connected to the upper surface of the firstchannel layer 760. The first gate electrode 733 may be disposed on thefirst channel layer 760.

The first channel layer 760 may comprise a recessed region recessed in adownward direction in the upper surface thereof. The first gateelectrode 733 may be disposed in the recessed region of the firstchannel layer 760.

The driving thin film transistor 830 according to an embodiment maycomprise a second gate electrode 833, a second channel layer 860, asecond source electrode 471, and a second drain electrode 472. Thesecond source electrode 471 may be electrically connected to a firstregion of the second channel layer 860. The second source electrode 471may be electrically connected to an upper surface of the second channellayer 860. The second drain electrode 472 may be electrically connectedto a second region of the second channel layer 860. The second drainelectrode 472 may be electrically connected to the upper surface of thesecond channel layer 860. The second gate electrode 833 may be disposedon the second channel layer 860.

The second channel layer 860 may comprise a recessed region recessed ina downward direction in the upper surface thereof. The second gateelectrode 833 may be disposed in the recessed region of the secondchannel layer 860.

The structures of the switching thin film transistor 730 and the drivingthin film transistor 830 may be similar to each other, and in thedescription of the driving thin film transistor 830, description ofcontents overlapping with those described with reference to theswitching thin film transistor 730 may be omitted.

The first channel layer 760 and the second channel layer 860 may beprovided with, for example, a Group III-V compound semiconductor. Forexample, the first channel layer 760 and the second channel layer 860may be provided with a semiconductor material having an empiricalformula of In_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The firstchannel layer 760 and the second channel layer 860 may comprise a singlelayer or multiple layers selected from, for example, GaN, AlN, AlGaN,InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and so on.The first channel layer 760 and the second channel layer 860 may beformed of different materials.

The first channel layer 760 and the second channel layer 860 may eachcomprise first nitride semiconductor layers 761 and 861 and secondnitride semiconductor layers 762 and 862. The first nitridesemiconductor layers 761 and 861 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). The second nitridesemiconductor layers 762 and 862 may be provided with, for example, asemiconductor material having an empirical formula ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1). A recessed regionrecessed downwardly may be provided in an upper surface of the secondnitride semiconductor layer 762 and 862. The first gate electrode 733may be disposed in the recessed region of the second nitridesemiconductor layer 762. An upper surface of the first gate electrode733 may be disposed higher than the highest surface of the secondnitride semiconductor layer 762. The first gate electrode 733 may be inSchottky contact with the second nitride semiconductor layer 762. Thesecond gate electrode 833 may be disposed in the recessed region of thesecond nitride semiconductor layer 862. An upper surface of the secondgate electrode 833 may be disposed higher than the highest surface ofthe second nitride semiconductor layer 862. The second gate electrode833 may be in Schottky contact with the second nitride semiconductorlayer 862. According to the first channel layer 760 and the secondchannel layer 860 according to an embodiment, the first nitridesemiconductor layer 761, 861 may comprise a GaN semiconductor layer, andthe second nitride semiconductor layer 762 and 862 may comprise an AlGaNsemiconductor layer.

The substrate 355 may comprise a transparent substrate. The substrate355 may be provided with a transparent substrate having a thickness of0.1 mm to 3 mm as an example. In addition, the thickness of thesubstrate 355 may be changed according to application and size of anapplied display device and may be selected within a thickness range of0.4 to 1.1 mm. For example, the substrate 355 may be provided in athickness of 0.6 to 0.8 mm. The substrate 355 may comprise at least onematerial selected from materials including silicon, glass, polyimide,and plastic. The substrate 355 may comprise a flexible substrate.

The substrate 355 is a substrate to be used in a transfer process, andserves to support the switching thin film transistor 730 and the drivingthin film transistor 830. In addition, the thin film transistorsubstrate according to an embodiment may comprise a bonding layer 350provided between the substrate 355 and the switching thin filmtransistor 730. The bonding layer 350 may be disposed between thesubstrate 355 and the driving thin film transistor 830.

The bonding layer 350 may comprise an organic material. The bondinglayer 350 may be provided with a transparent material. The bonding layer350 may be provided with, for example, a material having a transmittanceof 70% or more. The bonding layer 350 may comprise an organic insulatingmaterial. The bonding layer 350 may comprise at least one materialselected from the group consisting of acryl, benzocyclobutene (BCB),SU-8 polymer, and the like. The bonding layer 350 may be provided in athickness of 0.5 to 6 μm as an example. A thickness of the bonding layer350 may be different according to a type of a selected material and maybe provided in a thickness of 1 to 3 μm. In addition, the bonding layer350 may be provided in a thickness of 1.8 to 2.2 μm as an example.

The switching thin film transistor 730 according to an embodiment maycomprise a first source contact portion 331 disposed on the first regionof the first channel layer 760 and a first drain contact portion 332disposed on the second region of the first channel layer 760. The firstsource contact portion 331 may be disposed in contact with the firstregion of the first channel layer 760. The first drain contact portion332 may be disposed in contact with the second region of the firstchannel layer 760.

A switching thin film transistor 730 according to an embodiment maycomprise a first gate wiring 341 disposed on the first gate electrode733. The first gate wiring 341 may be electrically connected to thefirst gate electrode 733. A lower surface of the first gate wiring 341may be disposed in contact with an upper surface of the first gateelectrode 733.

The first source electrode 371 may be electrically connected to thefirst source contact portion 331. The first source electrode 371 may bedisposed in contact with an upper surface of the first source contactportion 331. For example, the first source electrode 371 may beelectrically connected to a first region of the first channel layer 760via the first source contact portion 331. The first drain electrode 372may be electrically connected to the first drain contact portion 332.The first drain electrode 372 may be disposed in contact with an uppersurface of the first drain contact portion 332. For example, the firstdrain electrode 372 may be electrically connected to a second region ofthe first channel layer 760 via the first drain contact portion 332.

The driving thin film transistor 830 according to an embodiment maycomprise a second source contact portion 431 disposed on the firstregion of the second channel layer 860 and a second drain contactportion 432 disposed on the second region of the second channel layer860. The second source contact portion 431 may be disposed in contactwith the first region of the second channel layer 860. The second draincontact portion 432 may be disposed in contact with the second region ofthe second channel layer 860.

A driving thin film transistor 830 according to an embodiment maycomprise a second gate wiring 441 disposed on the second gate electrode433. The second gate wiring 441 may be electrically connected to thesecond gate electrode 433. A lower surface of the second gate wiring 441may be disposed in contact with an upper surface of the second gateelectrode 433.

The second source electrode 471 may be electrically connected to thesecond source contact portion 431. The second source electrode 471 maybe disposed in contact with an upper surface of the second sourcecontact portion 431. For example, the second source electrode 471 may beelectrically connected to a first region of the second channel layer 860via the second source contact portion 431. The second drain electrode472 may be electrically connected to the second drain contact portion432. The second drain electrode 472 may be disposed in contact with anupper surface of the second drain contact portion 432. For example, thesecond drain electrode 472 may be electrically connected to a secondregion of the second channel layer 860 via the second drain contactportion 432.

The first source contact portion 331 and the first drain contact portion332 may be provided with a material in ohmic contact with the firstchannel layer 760. The first source contact portion 331 and the firstdrain contact portion 332 may comprise a material in ohmic contact withthe second nitride semiconductor layer 762. The second source contactportion 431 and the second drain contact portion 432 may be providedwith a material in ohmic contact with the second channel layer 860. Thesecond source contact portion 431 and the second drain contact portion432 may comprise a material in ohmic contact with the second nitridesemiconductor layer 862. For example, the first source contact portion331, the first drain contact portion 332, the second source contactportion 431, and the second drain contact portion 432 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first source contact portion331, the first drain contact portion 332, the second source contactportion 431, and the second drain contact portion 432 may be provided ina thickness of 0.1 to 1 μm as an example. The first source contactportion 331, the first drain contact portion 332, the second sourcecontact portion 431, and the second drain contact portion 432 do notneed to serve to spread a current as a layer for contacting with thefirst channel layer 760 and the second channel layer 860. Accordingly,the first source contact portion 331, the first drain contact portion332, the second source contact portion 431, and the second drain contactportion 432 may be provided in a thickness of 1 μm or less.

The first gate electrode 733 may be provided as a material in Schottkycontact with the first channel layer 760. The first gate electrode 733may be provided with a material which is in a Schottky contact with thesecond nitride semiconductor layer 762. The first gate electrode 733 maycomprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of nickel (Ni), platinum(Pt), gold (Au), and palladium (Pd), or an alloy thereof. For example,the Schottky contact may be implemented by plasma treatment of the firstchannel layer 760. In the plasma treatment, for example, fluorine (F)ion treatment may be applied. Accordingly, the switching thin filmtransistor 730 according to an embodiment may be provided with athreshold voltage by the Schottky contact and may have a normally offcharacteristic. When a voltage equal to or higher than the thresholdvoltage is applied to the first gate electrode 733, a channel formedunder the first gate electrode 733 is turned on to allow a current toflow the first channel layer 760.

The second gate electrode 833 may be provided as a material in Schottkycontact with the second channel layer 860. The second gate electrode 833may be provided with a material which is in a Schottky contact with thesecond nitride semiconductor layer 862. The second gate electrode 833may comprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of nickel (Ni), platinum(Pt), gold (Au), and palladium (Pd), or an alloy thereof. For example,the Schottky contact may be implemented by plasma treatment of thesecond channel layer 860. In the plasma treatment, for example, fluorine(F) ion treatment may be applied. Accordingly, the driving thin filmtransistor 830 according to an embodiment may be provided with athreshold voltage by the Schottky contact and may have a normally offcharacteristic. When a voltage equal to or higher than the thresholdvoltage is applied to the second gate electrode 833, a channel formedunder the second gate electrode 833 is turned on to allow a current toflow the second channel layer 860.

Meanwhile, according to the first channel layer 760 according to anembodiment, the first nitride semiconductor layer 761 may comprise a GaNsemiconductor layer, and the second nitride semiconductor layer 762 maycomprise an AlGaN semiconductor layer. As a thickness of the secondnitride semiconductor layer 762 is larger, the two-dimensional electrongas (2 DEG) is well formed, and thus it is difficult to make a normallyoff characteristic. In addition, when the thickness of the secondnitride semiconductor layer 762 is too thin, there is a problem thatgate leakage may be increased. Accordingly, it may be desirable that thethickness of the second nitride semiconductor layer 762 disposed underthe recessed region is provided in a thickness of 2 to 10 nm. Inaddition, as a method for reducing gate leakage, an insulator may bedisposed between the gate electrode 733 and the second nitridesemiconductor layer 762 to be provided in aMetal-Insulator-Semiconductor (MIS) structure. For example, the secondnitride semiconductor layer 762 in a region where the recess is notformed may be provided in a thickness of 15 to 25 nm. In addition, therecess may be provided in a width of 1.5 to 2.5 μm as an example.

Meanwhile, according to the second channel layer 860 according to anembodiment, the first nitride semiconductor layer 861 may comprise a GaNsemiconductor layer, and the second nitride semiconductor layer 862 maycomprise an AlGaN semiconductor layer. As a thickness of the secondnitride semiconductor layer 862 is larger, the two-dimensional electrongas (2 DEG) is well formed, and thus it is difficult to make a normallyoff characteristic. In addition, when the thickness of the secondnitride semiconductor layer 862 is too thin, there is a problem thatgate leakage may be increased. Accordingly, it may be desirable that thethickness of the second nitride semiconductor layer 862 disposed underthe recessed region is provided in a thickness of 2 to 10 nm. Inaddition, as a method for reducing gate leakage, an insulator may bedisposed between the gate electrode 833 and the second nitridesemiconductor layer 862 to be provided in aMetal-Insulator-Semiconductor (MIS) structure. For example, the secondnitride semiconductor layer 862 in a region where the recess is notformed may be provided in a thickness of 15 to 25 nm. In addition, therecess may be provided in a width of 1.5 to 2.5 μm as an example.

The first gate wiring 341 and the second gate wiring 441 may comprise asingle layer or multiple layers comprising at least one materialselected from the group consisting of aluminum (Al), an aluminum alloy(Al alloy), tungsten (W), copper (Cu), a copper alloy (Cu alloy),molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold (Au), agold alloy (Au alloy), chromium (Cr), titanium (Ti), a titanium alloy(Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi), andcopper/molybdenum titanium (Cu/MoTi). The first gate wiring 341 and thesecond gate wiring 441 may be provided in a thickness of 0.1 to 3 μm asan example. Since the first gate wiring 341 and the second gate wiring441 serves to sequentially apply a voltage to a plurality oftransistors, the first gate wiring 341 and the second gate wiring 441may be provided to be thicker than a thickness of the first gateelectrode 733 and the second gate electrode 833.

The first source electrode 371, the first drain electrode 372, thesecond source electrode 471, and the second drain electrode 472 maycomprise a single layer or multiple layers comprising at least onematerial selected from the group consisting of aluminum (Al), analuminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy (Cualloy), molybdenum (Mo), silver (Ag), a silver alloy (Ag alloy), gold(Au), a gold alloy (Au alloy), chromium (Cr), titanium (Ti), a titaniumalloy (Ti alloy), molybdenum tungsten (MoW), molybdenum titanium (MoTi),and copper/molybdenum titanium (Cu/MoTi). The first source electrode371, the first drain electrode 372, the second source electrode 471, andthe second drain electrode 472 may be provided in a thickness of 0.1 to3 μm as an example. Since the first source electrode 371 and the secondsource electrode 471 serve to sequentially apply a voltage to theplurality of transistors, the first source electrode 371 and the secondsource electrode 471 may be provided to be thicker than a thickness ofthe first source contact portion 331 and the second source contactportion 431. Also, the first drain electrode 372 and the second drainelectrode 472 may be provided to be thicker than a thickness of thefirst drain contact portion 332 and the second drain contact portion432.

The thin film transistor substrate according to an embodiment maycomprise a first passivation film 321 and 421 disposed on the firstchannel layer 760 and the second channel layer 860. The firstpassivation film 321 and 421 may be disposed on the second nitridesemiconductor layer 762 of the first channel layer 760 and the secondnitride semiconductor layer 862 of the second channel layer 860. A lowersurface of the first passivation film 321 and 421 may be disposed incontact with an upper surface of the second nitride semiconductor layer762 of the first channel layer 760 and the second nitride semiconductorlayer 862 of the second channel layer 860.

According to an embodiment, the first source contact portion 331 may bedisposed to pass through the first passivation film 321. The firstsource contact portion 331 may be disposed to be surrounded by the firstpassivation film 321. The first source contact portion 331 may bedisposed to pass through the first passivation film 321 and provided incontact with the first region of the first channel layer 760. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321. The first drain contact portion 332 may bedisposed to be surrounded by the first passivation film 321. The firstdrain contact portion 332 may be disposed to pass through the firstpassivation film 321 and provided in contact with the second region ofthe first channel layer 760.

According to an embodiment, the second source contact portion 431 may bedisposed to pass through the first passivation film 421. The secondsource contact portion 431 may be disposed to be surrounded by the firstpassivation film 421. The second source contact portion 431 may bedisposed to pass through the first passivation film 421 and provided incontact with the first region of the second channel layer 860. Thesecond drain contact portion 432 may be disposed to pass through thefirst passivation film 421. The second drain contact portion 432 may bedisposed to be surrounded by the first passivation film 421. The seconddrain contact portion 432 may be disposed to pass through the firstpassivation film 421 and provided in contact with the second region ofthe second channel layer 860.

The first passivation film 321 and 421 may be provided with aninsulating material. The first passivation film 321 and 421 may comprisea single layer or multiple layers comprising at least one material of asilicon-based oxide, a silicon-based nitride, a metal oxide comprisingAl₂O₃, and an organic insulating material as an example.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355 and the first passivation film 321 and421. The first gate electrode 733 may be disposed to pass through atleast one of the first passivation film 321 and the second passivationfilm 322. For example, the first gate electrode 733 may be disposed topass through the first passivation film 321 and the second passivationfilm 322. The first gate electrode 733 may pass through at least one ofthe first passivation film 321 and the second passivation film 322 andbe disposed in contact with the first channel layer 760. For example,the first gate electrode 733 may pass through the first passivation film321 and the second passivation film 322 and be disposed in contact withthe first channel layer 760. The first gate wiring 341 may be disposedon the second passivation film 322 and be electrically connected to thefirst gate electrode 733. The second gate electrode 833 may be disposedto pass through at least one of the first passivation film 321 and thesecond passivation film 322. For example, the second gate electrode 833may be disposed to pass through the first passivation film 321 and thesecond passivation film 322. The second gate electrode 833 may passthrough at least one of the first passivation film 321 and the secondpassivation film 322 and be disposed in contact with the second channellayer 860. For example, the second gate electrode 833 may pass throughthe first passivation film 321 and the second passivation film 322 andbe disposed in contact with the second channel layer 815. The secondgate wiring 441 may be disposed on the second passivation film 322 andbe electrically connected to the second gate electrode 833.

The second passivation film 322 may be provided with an insulatingmaterial. The second passivation film 322 may comprise a single layer ormultiple layers including at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide including Al₂O₃, and anorganic insulating material as an example.

According to an embodiment, a third passivation film 323 may be disposedon the second passivation film 322. The third passivation film 323 maybe disposed on the second passivation film 322, the first gate wiring341, and the second gate wiring 342.

The first gate wiring 341 may be disposed in contact with the first gateelectrode 733 thereon and provided to be surrounded by the thirdpassivation film 323. The second gate wiring 441 may be disposed incontact with the second gate electrode 833 thereon and provided to besurrounded by the third passivation film 323.

The first source electrode 371 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the first source contact portion 331. The first sourceelectrode 371 may comprise a first region disposed on the thirdpassivation film 323. The first source electrode 371 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The first drain electrode 372 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the first drain contact portion332. The first drain electrode 372 may comprise a first region disposedon the third passivation film 323. The first drain electrode 372 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

The second source electrode 471 may pass through the second passivationfilm 322 and the third passivation film 323 and be electricallyconnected to the second source contact portion 431. The second sourceelectrode 471 may comprise a first region disposed on the thirdpassivation film 323. The second source electrode 471 may comprise asecond region passing through the third passivation film 323 and thesecond passivation film 322. The second drain electrode 472 may passthrough the second passivation film 322 and the third passivation film323 and be electrically connected to the second drain contact portion432. The second drain electrode 472 may comprise a first region disposedon the third passivation film 323. The second drain electrode 472 maycomprise a second region passing through the third passivation film 323and the second passivation film 322.

The third passivation film 323 may comprise an insulating material. Forexample, the third passivation film 323 may comprise a single layer ormultiple layers comprising at least one material among a silicon-basedoxide, a silicon nitride, a metal oxide containing Al₂O₃, and an organicinsulator.

The thin film transistor substrate according to an embodiment maycomprise a fourth passivation film 324 disposed on the third passivationfilm 323. The fourth passivation film 324 may be disposed on the firstsource electrode 371, the first drain electrode 372, the second sourceelectrode 471, and the second drain electrode 472.

For example, the fourth passivation film 324 may comprise a single layeror multiple layers containing at least one material of a silicon-basedoxide, a silicon-based nitride, a metal oxide containing Al₂O₃, and anorganic insulating material.

The thin film transistor substrate according to an embodiment maycomprise a lower electrode 486 disposed on the driving thin filmtransistor 830. The lower electrode 486 may be electrically connected tothe driving thin film transistor 830. The lower electrode 486 may beelectrically connected to the second drain electrode 472 of the drivingthin film transistor 830. The lower electrode 486 may be disposed on thefourth passivation film 324. The lower electrode 486 may be electricallyconnected to the second drain electrode 472 through a contact holeprovided in the fourth passivation film 324. A lower surface of thelower electrode 486 may be disposed in contact with an upper surface ofthe second drain electrode 472.

In addition, the thin film transistor substrate according to anembodiment may comprise a fifth passivation film 325 disposed on thefourth passivation film 324. The light-emitting layer 488 may bedisposed on the lower electrode 486. An upper electrode 487 may bedisposed on the light-emitting layer 488. The light-emitting layer 488and the upper electrode 487 may be disposed on the fifth passivationfilm 325. A first region of the light-emitting layer 488 may be disposedon the fifth passivation film 325, and a second region of thelight-emitting layer 488 may be disposed in contact with an uppersurface of the lower electrode 486 through a contact hole provided inthe fifth passivation film 325. The light-emitting layer 488 may emitlight of any one of red, green, blue, and white as an example. Thelight-emitting layer 488 may be provided with an organic material as anexample.

The lower electrode 486 and the upper electrode 487, for example, maycomprise one material selected from ITO, ITO/Ag, ITO/Ag/ITO, andITO/Ag/IZO, or an alloy containing the material. The lower electrode 486and the upper electrode 487 may comprise different materials. One of theupper electrode 486 and the lower electrode 487 may be formed of atransparent electrode, and light emitted from the light-emitting layer488 in a direction of the transparent electrode may be emitted to theoutside.

The thin film transistor substrate according to an embodiment maycomprise a first black matrix 340 between the substrate 355 and thefirst channel layer 760. A width of the first channel layer 760 may beprovided to be equal to a width of the first black matrix 340. The firstblack matrix 340 may be provided in a single layer or multiple layersincluding at least one material selected from among a Si-based material,a Ga-based material, an Al-based material, and an organic material. Thefirst black matrix 340 may block light incident on the switching thinfilm transistor 730. Accordingly, it is possible to prevent theswitching thin film transistor 730 from deteriorating due to a photocurrent or the like.

The thin film transistor substrate according to an embodiment maycomprise a second black matrix 440 between the substrate 355 and thesecond channel layer 860. A width of the second channel layer 860 may beprovided to be equal to a width of the second black matrix 440. Thesecond black matrix 440 may be provided in a single layer or multiplelayers including at least one material selected from among a Si-basedmaterial, a Ga-based material, an Al-based material, and an organicmaterial. The second black matrix 440 may block light incident on thedriving thin film transistor 830. Accordingly, it is possible to preventthe driving thin film transistor 830 from deteriorating due to a photocurrent or the like.

According to an embodiment, the bonding layer 350 may be disposedbetween the substrate 355 and the first channel layer 760. The bondinglayer 350 may be disposed between the substrate 355 and the first blackmatrix 340. The bonding layer 350 may be disposed between the substrate355 and the second channel layer 860. The bonding layer 350 may bedisposed between the substrate 355 and the second black matrix 440. Forexample, the bonding layer 350 may be disposed on an entire region ofthe substrate 355.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 51 is a view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 51, in the description of the thin filmtransistor substrate according to an embodiment, description of a partoverlapping with those described with reference to FIGS. 1 to 50 may beomitted. An embodiment shown in FIG. 51 differs from that of FIG. 50 inthe bonding layer structure.

As shown in FIG. 51, a first bonding layer 353 and a second bondinglayer 453 may be provided on the substrate 355. The first bonding layer353 may be disposed between the substrate 355 and the first black matrix340. For example, a width of the first bonding layer 353 may be providedto be equal to a width of the first black matrix 340. For example, thewidth of the first bonding layer 353 may be provided to be equal to awidth of the first channel layer 760. The second bonding layer 453 maybe disposed between the substrate 355 and the second black matrix 440.For example, a width of the second bonding layer 453 may be provided tobe equal to a width of the second black matrix 440. For example, thewidth of the second bonding layer 453 may be provided to be equal to awidth of the second channel layer 860.

According to an embodiment, a second passivation film 322 may bedisposed on the substrate 355. A lower surface of the second passivationfilm 322 may be disposed in contact with an upper surface of thesubstrate 355. In a region where the first bonding layer 350 is notprovided, the second passivation film 322 may be disposed in directcontact with the substrate 355. In a region where the second bondinglayer 450 is not provided, the second passivation film 322 may bedisposed in direct contact with the substrate 355.

As described above, according to the embodiment shown in FIG. 51, ascompared with the embodiment shown in FIG. 50, since the secondpassivation film 322 and the substrate 355 may be disposed in directcontact with each other, a layer provided between the second passivationfilm 322 and the substrate 355 (for example, an illustrated bondinglayer in FIG. 50) may be eliminated. Accordingly, according to theembodiment, since an interface between different material layers isreduced on a light path where light travels, light loss due toreflection/refraction at the interface may be reduced.

The first bonding layer 353 and the second bonding layer 453 accordingto an embodiment may comprise at least one of a reflective layer, ametal bonding layer, an organic bonding layer, and an insulating layeras an example. The reflective layer may be disposed on the substrate355, the metal bonding layer may be disposed on the reflective layer,and the insulating layer may be disposed on the metal bonding layer. Forexample, the first bonding layer 353 and the second bonding layer 453may comprise at least one of the metal bonding layer and the organicbonding layer, and the reflective layer and the insulating layer may becomprised selectively.

The insulating layer may complement the leakage characteristics of thefirst channel layer 760 and the second channel layer 860. For example,the insulating layer may comprise a single layer or multiple layersincluding at least one material of a silicon-based oxide, asilicon-based nitride, a metal oxide including Al₂O₃, and an organicinsulating material as an example.

The metal bonding layer or the organic bonding layer may be provided forbonding with the substrate 355 disposed thereunder. For example, themetal bonding layer may comprise at least one material selected from thegroup consisting of gold (Au), tin (Sn), indium (In), nickel (Ni),silver (Ag), and copper (Cu), or an alloy thereof. For example, theorganic bonding layer may comprise at least one material selected fromthe group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, andthe like.

The reflective layer may reduce light absorption in the bonding layer.For example, the reflective layer may comprise at least one materialselected from the group consisting of aluminum (Al), silver (Ag), andrhodium (Rh), or an alloy thereof. The reflective layer may be providedwith a material having a reflection characteristic of more than 60% asan example.

Meanwhile, according to an embodiment, for example, when the firstbonding layer 353 and the second bonding layer 453 comprise the metalbonding layer and the reflective layer, the first black matrix 340 andthe second black matrix 440 may be omitted.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

According to an embodiment, a high quality semiconductor layer may beformed by using the growth substrate and a thin film transistorsubstrate having an excellent electron mobility may be provided byapplying a transfer process by using the support substrate.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 52 is view illustrating still another example of a thin filmtransistor substrate according to an embodiment of the presentinvention. Referring to FIG. 52, in the description of the thin filmtransistor substrate according to the embodiment, description ofcontents overlapping with those described with reference to FIGS. 1 to51 may be omitted. An embodiment shown in FIG. 52 differs from that ofFIG. 50 in that a transfer process is not applied and a thin filmtransistor is provided on a growth substrate.

As shown in FIG. 52, the thin film transistor substrate according to theembodiment may comprise a growth substrate 310 as a substrate instead ofa support substrate used in the transfer process. For example, thegrowth substrate 310 may comprise at least one of group consisting ofsapphire, SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge.

A first black matrix 345 and a second black matrix 445 may be disposedon the growth substrate 310. The first black matrix 345 is disposed onthe growth substrate 310 and may prevent light from being incident onthe first channel layer 760. The first black matrix 345 may be providedwith a material that absorbs or reflects visible rays as an example.Thus, according to the embodiment, light is incident on the firstchannel layer 760 and it is possible to prevent a switching thin filmtransistor 730 from being deteriorated due to a photo current or thelike. The second black matrix 445 is disposed on the growth substrate310 and may prevent light from being incident on the second channellayer 860. The second black matrix 445 may be provided with a materialthat absorbs or reflects visible rays as an example. Thus, according tothe embodiment, light is incident on the second channel layer 860 and itis possible to prevent a driving thin film transistor 830 from beingdeteriorated due to a photo current or the like.

For example, the first black matrix 345 and the second black matrix 445may be provided in a single layer or multiple layers including at leastone material selected from among a Si-based material, a Ga-basedmaterial, an Al-based material, and an organic material. The first blackmatrix 345 and the second black matrix 445 may selectively comprise amaterial such as Si, GaAs, or the like.

According to an embodiment, a first buffer layer 347 may be provided onthe first black matrix 345. The first buffer layer 347 may be providedbetween the first black matrix 345 and the first channel layer 760. Thefirst buffer layer 347 may help a growth of a nitride semiconductorlayer constituting the first channel layer 760. A second buffer layer447 may be provided on the second black matrix 445. The second bufferlayer 447 may be provided between the second black matrix 445 and thesecond channel layer 860. The second buffer layer 447 may help a growthof a nitride semiconductor layer constituting the second channel layer860. For example, the first buffer layer 347 and the second buffer layer447 may comprise a single layer or multiple layers including at leastone material selected from the group consisting of AlN, AlInN, andAlGaN.

For example, a width of the first black matrix 345 may be provided to beequal to a width of the first buffer layer 347. For example, the widthof the first black matrix 345 may be provided to be equal to a width ofthe first channel layer 760. The width of the first buffer layer 347 maybe provided to be equal to the width of the first channel layer 760. Awidth of the second black matrix 445 may be provided to be equal to awidth of the second buffer layer 447. For example, the width of thesecond black matrix 445 may be provided to be equal to a width of thesecond channel layer 860. The width of the second buffer layer 447 maybe provided to be equal to the width of the second channel layer 860.

According to an embodiment, the second passivation film 322 may bedisposed on the growth substrate 310. A lower surface of the secondpassivation film 322 may be disposed in contact with an upper surface ofthe growth substrate 310. In a region where the first black matrix 345and the second black matrix 445 is not provided, the second passivationfilm 322 may be disposed in direct contact with the growth substrate310.

According to the thin film transistor substrate according to anembodiment, a high carrier mobility may be implemented by providing thethin film transistor comprising the nitride-based semiconductor layer.For example, an electron mobility (cm²/Vs) of the thin film transistorvaries depending on a material used as a channel layer, it is reportedthat an amorphous silicon semiconductor has an electron mobility of 1,an oxide semiconductor has that of 10 to 80, and a polysiliconsemiconductor has that of 100 or less. However, the thin film transistorcomprising the nitride-based semiconductor layer according to anembodiment has been measured to have an electron mobility of 1500.Accordingly, the thin film transistor comprising the nitride-basedsemiconductor layer according to an embodiment may be implemented tohave an electron mobility 15 times or higher than that of the thin filmtransistor to which the polysilicon semiconductor is applied.

Therefore, according to the thin film transistor substrate, the displaypanel and the display device comprising the same, a high resolution canbe realized and a smooth moving picture can be reproduced by providing ahigh carrier mobility.

FIG. 53 is a block diagram illustrating an example of a display devicecomprising a thin film transistor substrate according to an embodimentof the present invention.

As shown in FIG. 53, the display device according to an embodiment maycomprise a display panel 2100 and a panel driver 2300.

The display panel 2100 may comprise any one of the thin film transistorsubstrates described with reference to FIGS. 42 to 52. The panel driver2300 may provide a driving signal to the display panel 2100. The paneldriver 2300 may control light transmittance of a plurality of pixelsprovided in the display panel 2100, so that an image may be displayed onthe display panel 2100.

The features, structures, effects and the like described in theembodiments are comprised in at least one embodiment of the presentinvention and are not necessarily limited to only one embodiment.Furthermore, the features, structures, effects and the like illustratedin the embodiments may be combined or modified with other embodiments bythose skilled in the art to which the embodiments belong. Accordingly,it is to be understood that such combination and modification arecomprised in the scope of the present invention.

The above description of the embodiments is merely examples and does notlimit the present invention. It would be apparent to those of ordinaryskill in the art that the present invention may be easily embodied inmany different forms without changing the technical idea or essentialfeatures thereof. For example, elements of the exemplary embodimentsdescribed herein may be modified and realized. Also, it should beconstrued that differences related to such changes and applications arecomprised in the scope of the present invention defined in the appendedclaims.

INDUSTRIAL APPLICABILITY

According to an embodiment, a thin film transistor substrate, a displaypanel and a display device comprising the same, have an advantage ofrealizing a high resolution and reproducing a smooth moving picture byproviding a high carrier mobility.

The invention claimed is:
 1. A thin film transistor substratecomprising: a substrate; a switching thin film transistor disposed onthe substrate, the switching thin film transistor comprising a firstchannel layer including a nitride-based semiconductor layer, a firstsource electrode electrically connected to a first region of the firstchannel layer, a first drain electrode electrically connected to asecond region of the first channel layer, a first gate electrodedisposed on the first channel layer, and a first depletion forming layerdisposed between the first channel layer and the first gate electrode;and a driving thin film transistor disposed on the substrate, thedriving thin film transistor comprising a second channel layer includinga nitride-based semiconductor layer, a second source electrodeelectrically connected to a first region of the second channel layer, asecond drain electrode electrically connected to a second region of thesecond channel layer, a second gate electrode disposed on the secondchannel layer, and a second depletion forming layer disposed between thesecond channel layer and the second gate electrode.
 2. The thin filmtransistor substrate of claim 1, wherein the first channel layer and thesecond channel layer comprise a semiconductor layer ofIn_(x)Al_(y)Ga_(1-x-y)N (0≥x≥1, 0≥y≥1, 0≥x+y≥1).
 3. The thin filmtransistor substrate of claim 1, wherein the first channel layercomprises a first GaN semiconductor layer, and a first AlGaNsemiconductor layer disposed between the first GaN semiconductor layerand the first depletion forming layer, and wherein the second channellayer comprises a second GaN semiconductor layer, and a second AlGaNsemiconductor layer disposed between the second GaN semiconductor layerand the second depletion forming layer.
 4. The thin film transistorsubstrate of claim 1, further comprising: a first black matrix disposedbetween the substrate and the first channel layer, and a second blackmatrix disposed between the substrate and the second channel layer. 5.The thin film transistor substrate of claim 1, further comprising: afirst bonding layer disposed between the substrate and the first channellayer, and a second bonding layer disposed between the substrate and thesecond channel layer.
 6. The thin film transistor substrate of claim 1,further comprising a bonding layer disposed between the substrate andthe first channel layer and between the substrate and the second channellayer, wherein the bonding layer is disposed on an entire area of thesubstrate.
 7. The thin film transistor substrate of claim 1, wherein thesubstrate is a growth substrate.
 8. The thin film transistor substrateof claim 1, wherein the firsts drain electrode of the switching thinfilm transistor is electrically connected to the second gate electrodeof the driving thin film transistor.
 9. The thin film transistorsubstrate of claim 1, further comprising: a first passivation filmdisposed on the first channel layer; a second passivation film disposedon the substrate and the first passivation film; a first source contactportion passing through the first passivation film, disposed in contactwith the first region of the first channel layer, and electricallyconnected to the first source electrode; and a first drain contactportion passing through the first passivation film, disposed in contactwith the second region of the first channel layer, and electricallyconnected to the first drain electrode.
 10. A display panel comprising athin film transistor substrate according to claim
 1. 11. A displaydevice comprising: a display panel comprising a thin film transistorsubstrate according to claim 1; and a panel driver configured to drivethe display panel.
 12. The thin film transistor substrate of claim 3,wherein the first depletion forming layer and the second depletionforming layer comprise a GaN semiconductor layer doped with a p-typedopant or an AlGaN semiconductor layer doped with a p-type dopant. 13.The thin film transistor substrate of claim 4, wherein a width of thefirst channel layer is equal to a width of the first black matrix, andwherein a width of the second channel layer is equal to a width of thesecond black matrix.
 14. The thin film transistor substrate of claim 4,wherein each of the first black matrix and the second black matrix is asingle layer or multiple layers including at least one material selectedfrom among an Si-based material, a Ga-based material, an Al-basedmaterial, and an organic material.
 15. The thin film transistorsubstrate of claim 5, wherein each of the first bonding layer and thesecond bonding layer comprises a reflective layer disposed on thesubstrate, a metal bonding layer disposed on the reflective layer, andan insulating layer disposed on the metal bonding layer.
 16. The thinfilm transistor substrate of claim 5, wherein a width of the firstchannel layer is equal to a width of the first bonding layer, andwherein a width of the second channel layer is equal to a width of thesecond bonding layer.
 17. The thin film transistor substrate of claim 9,wherein the first gate electrode passes through the first passivationfilm and the second passivation film, and is disposed in contact withthe first depletion forming layer.
 18. The thin film transistorsubstrate of claim 9, further comprising a gate wiring disposed on thesecond passivation film and electrically connected to the first gateelectrode.
 19. The thin film transistor substrate of claim 9, wherein aside surface of the first source contact portion and a side surface ofthe firsts drain contact portion are disposed to face each other,wherein the first depletion forming layer is disposed to be extending inone direction between the side surface of the first source contactportion and the side surface of the first drain contact portion, andwherein a length of the first depletion forming layer disposed to beextending in the one direction is longer than a length of the sidesurface of the first source contact portion.
 20. The thin filmtransistor substrate of claim 18, further comprising a third passivationfilm on the second passivation film and the gate wiring, wherein thefirst source electrode and the first drain electrode are disposed on thethird passivation film.